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Revert "[Deepin Kernel SIG] ethernet: release motorcomm yt6801 v1.0.29" #500

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merged 2 commits into from
Nov 27, 2024
Merged

Revert "[Deepin Kernel SIG] ethernet: release motorcomm yt6801 v1.0.29" #500

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91ea230
Revert "ethernet: release motorcomm yt6801 v1.0.29"
opsiff Nov 27, 2024
e4514bd
Revert "ethernet: release motorcomm yt6801 v1.0.28"
opsiff Nov 27, 2024
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2 changes: 1 addition & 1 deletion drivers/net/ethernet/motorcomm/yt6801/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -12,4 +12,4 @@ yt6801-objs := fuxi-gmac-common.o \
fuxi-gmac-pci.o \
fuxi-gmac-phy.o \
fuxi-efuse.o \
fuxi-gmac-ioctl.o
fuxi-gmac-debugfs.o
201 changes: 95 additions & 106 deletions drivers/net/ethernet/motorcomm/yt6801/fuxi-efuse.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@

/* read patch per index. */
bool fxgmac_read_patch_from_efuse_per_index(struct fxgmac_pdata *pdata,
u8 index, u32 __far *offset, u32 __far *value)
u8 index, u32 *offset, u32 *value)
{
unsigned int wait, i;
u32 regval = 0;
bool succeed = false;

if (index >= FXGMAC_EFUSE_MAX_ENTRY) {
if (index >= FUXI_EFUSE_MAX_ENTRY) {
FXGMAC_PR("Reading efuse out of range, index %d\n", index);
return false;
}
Expand Down Expand Up @@ -105,95 +105,6 @@ bool fxgmac_read_patch_from_efuse_per_index(struct fxgmac_pdata *pdata,
return succeed;
}


bool fxgmac_read_mac_subsys_from_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr,
u32 *subsys, u32 *revid)
{
u32 offset = 0, value = 0;
u32 machr = 0, maclr = 0;
bool succeed = true;
u8 index = 0;

for (index = 0;; index++) {
if (!fxgmac_read_patch_from_efuse_per_index(pdata, index,
&offset, &value)) {
succeed = false;
break; /* reach the last item. */
}
if (0x00 == offset) {
break; /* reach the blank. */
}
if (MACA0LR_FROM_EFUSE == offset) {
maclr = value;
}
if (MACA0HR_FROM_EFUSE == offset) {
machr = value;
}

if ((0x08 == offset) && revid) {
*revid = value;
}
if ((0x2C == offset) && subsys) {
*subsys = value;
}
}
if (mac_addr) {
mac_addr[5] = (u8)(maclr & 0xFF);
mac_addr[4] = (u8)((maclr >> 8) & 0xFF);
mac_addr[3] = (u8)((maclr >> 16) & 0xFF);
mac_addr[2] = (u8)((maclr >> 24) & 0xFF);
mac_addr[1] = (u8)(machr & 0xFF);
mac_addr[0] = (u8)((machr >> 8) & 0xFF);
}

return succeed;
}


bool fxgmac_efuse_read_data(struct fxgmac_pdata *pdata, u32 offset, u32 __far *value)
{
bool succeed = false;
unsigned int wait;
u32 reg_val = 0;

if (value) {
*value = 0;
}

reg_val = FXGMAC_SET_REG_BITS(reg_val, EFUSE_OP_ADDR_POS,
EFUSE_OP_ADDR_LEN, offset);
reg_val = FXGMAC_SET_REG_BITS(reg_val, EFUSE_OP_START_POS,
EFUSE_OP_START_LEN, 1);
reg_val = FXGMAC_SET_REG_BITS(reg_val, EFUSE_OP_MODE_POS,
EFUSE_OP_MODE_LEN,
EFUSE_OP_MODE_ROW_READ);
writereg(pdata->pAdapter, reg_val, pdata->base_mem + EFUSE_OP_CTRL_0);
wait = 1000;
while (wait--) {
usleep_range_ex(pdata->pAdapter, 20, 50);
reg_val = readreg(pdata->pAdapter,
pdata->base_mem + EFUSE_OP_CTRL_1);
if (FXGMAC_GET_REG_BITS(reg_val, EFUSE_OP_DONE_POS,
EFUSE_OP_DONE_LEN)) {
succeed = true;
break;
}
}

if (succeed) {
if (value) {
*value = FXGMAC_GET_REG_BITS(reg_val,
EFUSE_OP_RD_DATA_POS,
EFUSE_OP_RD_DATA_LEN);
}
} else {
FXGMAC_PR("Fail to reading efuse Byte%d\n", offset);
}

return succeed;
}

#ifndef COMMENT_UNUSED_CODE_TO_REDUCE_SIZE
bool fxgmac_read_patch_from_efuse(struct fxgmac_pdata *pdata, u32 offset,
u32 *value) /* read patch per index. */
{
Expand All @@ -209,7 +120,7 @@ bool fxgmac_read_patch_from_efuse(struct fxgmac_pdata *pdata, u32 offset,
return false;
}

for (index = 0; index < FXGMAC_EFUSE_MAX_ENTRY; index++) {
for (index = 0; index < FUXI_EFUSE_MAX_ENTRY; index++) {
if (!fxgmac_read_patch_from_efuse_per_index(
pdata, index, &reg_offset, &reg_val)) {
succeed = false;
Expand All @@ -235,7 +146,7 @@ bool fxgmac_write_patch_to_efuse_per_index(struct fxgmac_pdata *pdata, u8 index,
u32 reg_val;
bool succeed = false;
u32 cur_reg, cur_val;
u8 max_index = FXGMAC_EFUSE_MAX_ENTRY;
u8 max_index = FUXI_EFUSE_MAX_ENTRY;

if (offset >> 16) {
FXGMAC_PR(
Expand All @@ -246,7 +157,7 @@ bool fxgmac_write_patch_to_efuse_per_index(struct fxgmac_pdata *pdata, u8 index,

fxgmac_efuse_read_data(pdata, EFUSE_LED_ADDR, &reg_val);
if (EFUSE_LED_COMMON_SOLUTION == reg_val) {
max_index = FXGMAC_EFUSE_MAX_ENTRY_UNDER_LED_COMMON;
max_index = FUXI_EFUSE_MAX_ENTRY_UNDER_LED_COMMON;
}

if (index >= max_index) {
Expand Down Expand Up @@ -459,16 +370,55 @@ bool fxgmac_write_patch_to_efuse(struct fxgmac_pdata *pdata, u32 offset,
return succeed;
}

bool fxgmac_read_mac_subsys_from_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr,
u32 *subsys, u32 *revid)
{
u32 offset = 0, value = 0;
u32 machr = 0, maclr = 0;
bool succeed = true;
u8 index = 0;

for (index = 0;; index++) {
if (!fxgmac_read_patch_from_efuse_per_index(pdata, index,
&offset, &value)) {
succeed = false;
break; /* reach the last item. */
}
if (0x00 == offset) {
break; /* reach the blank. */
}
if (MACA0LR_FROM_EFUSE == offset) {
maclr = value;
}
if (MACA0HR_FROM_EFUSE == offset) {
machr = value;
}

if ((0x08 == offset) && revid) {
*revid = value;
}
if ((0x2C == offset) && subsys) {
*subsys = value;
}
}
if (mac_addr) {
mac_addr[5] = (u8)(maclr & 0xFF);
mac_addr[4] = (u8)((maclr >> 8) & 0xFF);
mac_addr[3] = (u8)((maclr >> 16) & 0xFF);
mac_addr[2] = (u8)((maclr >> 24) & 0xFF);
mac_addr[1] = (u8)(machr & 0xFF);
mac_addr[0] = (u8)((machr >> 8) & 0xFF);
}

return succeed;
}

bool fxgmac_write_mac_subsys_to_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr,
u32 *subsys, u32 *revid)
{
#ifdef DBG
u32 machr = 0, maclr = 0;
#endif
u32 pcie_cfg_ctrl = PCIE_CFG_CTRL_DEFAULT_VAL;
u32 machr = 0, maclr = 0, pcie_cfg_ctrl = PCIE_CFG_CTRL_DEFAULT_VAL;
bool succeed = true;
if (mac_addr) {
#ifdef DBG
machr = readreg(pdata->pAdapter,
pdata->base_mem + MACA0HR_FROM_EFUSE);
maclr = readreg(pdata->pAdapter,
Expand All @@ -477,7 +427,7 @@ bool fxgmac_write_mac_subsys_to_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr,
(machr >> 8) & 0xFF, machr & 0xFF, (maclr >> 24) & 0xFF,
(maclr >> 16) & 0xFF, (maclr >> 8) & 0xFF,
maclr & 0xFF);
#endif

if (!fxgmac_write_patch_to_efuse(pdata, MACA0HR_FROM_EFUSE,
(((u32)mac_addr[0]) << 8) |
mac_addr[1])) {
Expand Down Expand Up @@ -523,13 +473,10 @@ bool fxgmac_write_mac_subsys_to_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr,

bool fxgmac_write_mac_addr_to_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr)
{
#ifdef DBG
u32 machr = 0, maclr = 0;
#endif
bool succeed = true;

if (mac_addr) {
#ifdef DBG
machr = readreg(pdata->pAdapter,
pdata->base_mem + MACA0HR_FROM_EFUSE);
maclr = readreg(pdata->pAdapter,
Expand All @@ -538,7 +485,7 @@ bool fxgmac_write_mac_addr_to_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr)
(machr >> 8) & 0xFF, machr & 0xFF, (maclr >> 24) & 0xFF,
(maclr >> 16) & 0xFF, (maclr >> 8) & 0xFF,
maclr & 0xFF);
#endif

if (!fxgmac_write_patch_to_efuse(pdata, MACA0HR_FROM_EFUSE,
(((u32)mac_addr[0]) << 8) |
mac_addr[1])) {
Expand Down Expand Up @@ -638,6 +585,49 @@ bool fxgmac_efuse_load(struct fxgmac_pdata *pdata)
return succeed;
}

bool fxgmac_efuse_read_data(struct fxgmac_pdata *pdata, u32 offset, u32 *value)
{
bool succeed = false;
unsigned int wait;
u32 reg_val = 0;

if (value) {
*value = 0;
}

reg_val = FXGMAC_SET_REG_BITS(reg_val, EFUSE_OP_ADDR_POS,
EFUSE_OP_ADDR_LEN, offset);
reg_val = FXGMAC_SET_REG_BITS(reg_val, EFUSE_OP_START_POS,
EFUSE_OP_START_LEN, 1);
reg_val = FXGMAC_SET_REG_BITS(reg_val, EFUSE_OP_MODE_POS,
EFUSE_OP_MODE_LEN,
EFUSE_OP_MODE_ROW_READ);
writereg(pdata->pAdapter, reg_val, pdata->base_mem + EFUSE_OP_CTRL_0);
wait = 1000;
while (wait--) {
usleep_range_ex(pdata->pAdapter, 20, 50);
reg_val = readreg(pdata->pAdapter,
pdata->base_mem + EFUSE_OP_CTRL_1);
if (FXGMAC_GET_REG_BITS(reg_val, EFUSE_OP_DONE_POS,
EFUSE_OP_DONE_LEN)) {
succeed = true;
break;
}
}

if (succeed) {
if (value) {
*value = FXGMAC_GET_REG_BITS(reg_val,
EFUSE_OP_RD_DATA_POS,
EFUSE_OP_RD_DATA_LEN);
}
} else {
FXGMAC_PR("Fail to reading efuse Byte%d\n", offset);
}

return succeed;
}

bool fxgmac_efuse_write_oob(struct fxgmac_pdata *pdata)
{
bool succeed = false;
Expand Down Expand Up @@ -1351,5 +1341,4 @@ bool fxgmac_read_led_setting_from_efuse(struct fxgmac_pdata *pdata)
}

return bsucceed;
}
#endif
}
12 changes: 4 additions & 8 deletions drivers/net/ethernet/motorcomm/yt6801/fuxi-efuse.h
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Original file line number Diff line number Diff line change
@@ -1,15 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2021 Motorcomm Corporation. */

#ifndef __FXGMAC_EFUSE_H__
#define __FXGMAC_EFUSE_H__
#ifndef __FUXI_EFUSE_H__
#define __FUXI_EFUSE_H__

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WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit description?)

bool fxgmac_read_patch_from_efuse_per_index(struct fxgmac_pdata *pdata, u8 index, u32 __far *offset, u32 __far *value); /* read patch per 0-based index. */
bool fxgmac_read_mac_subsys_from_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr, u32 *subsys, u32 *revid);
bool fxgmac_efuse_read_data(struct fxgmac_pdata *pdata, u32 offset, u32 __far *value);

#ifndef COMMENT_UNUSED_CODE_TO_REDUCE_SIZE
bool fxgmac_read_patch_from_efuse(struct fxgmac_pdata *pdata, u32 offset, u32 *value); /* read patch per register offset. */
bool fxgmac_read_patch_from_efuse_per_index(struct fxgmac_pdata *pdata, u8 index, u32 *offset, u32 *value); /* read patch per 0-based index. */
bool fxgmac_write_patch_to_efuse(struct fxgmac_pdata *pdata, u32 offset, u32 value);
bool fxgmac_write_patch_to_efuse_per_index(struct fxgmac_pdata *pdata, u8 index, u32 offset, u32 value);
bool fxgmac_read_mac_subsys_from_efuse(struct fxgmac_pdata *pdata, u8 *mac_addr, u32 *subsys, u32 *revid);
Expand All @@ -24,6 +21,5 @@ bool fxgmac_efuse_write_oob(struct fxgmac_pdata *pdata);
bool fxgmac_efuse_write_led(struct fxgmac_pdata *pdata, u32 value);
bool fxgmac_read_led_setting_from_efuse(struct fxgmac_pdata *pdata);
bool fxgmac_write_led_setting_to_efuse(struct fxgmac_pdata *pdata);
#endif

#endif /* __FXGMAC_EFUSE_H__ */
#endif /* __FUXI_EFUSE_H__ */
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