[Intel-SIG] MTL x86/perf updates sync with upstream (6.9) #243
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mainline:c3dd1995620cdcd65cf4944c4164b0dbc16e557c severity: Moderate upstream commit c3dd199 ("x86/smp: Export symbol cpu_clustergroup_mask()") Intel cstate PMU driver will invoke the topology_cluster_cpumask() to retrieve the CPU mask of a cluster. A modpost error is triggered since the symbol cpu_clustergroup_mask is not exported. Intel-SIG: commit c3dd199 ("x86/smp: Export symbol cpu_clustergroup_mask()") Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:090e3bec01763e415bccae445f5bfe3d0c61b629 severity: Moderate upstream commit 090e3be ("x86/cpu: Add model number for Intel Clearwater Forest processor") Server product based on the Atom Darkmont core. Intel-SIG: commit 090e3be ("x86/cpu: Add model number for Intel Clearwater Forest processor") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:8a8a9c9047d1089598bdb010ec44d7f14b4f9203 severity: Moderate upstream commit 8a8a9c9 ("x86/cpu: Add model number for another Intel Arrow Lake mobile processor") This one is the regular laptop CPU. Intel-SIG: commit 8a8a9c9 ("x86/cpu: Add model number for another Intel Arrow Lake mobile processor") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:a9d0adce69075192961f3be466c4810a21b7bc9e severity: Moderate upstream commit a9d0adc ("x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86") Refactor struct cpuinfo_x86 so that the vendor, family, and model fields are overlaid in a union with a 32-bit field that combines all three (together with a one byte reserved field in the upper byte). This will make it easy, cheap, and reliable to check all three values at once. See https://lore.kernel.org/r/Zgr6kT8oULbnmEXx@agluck-desk3 for why the ordering is (low-to-high bits): (vendor, family, model) [ bp: Move comments over the line, add the backstory about the particular order of the fields. ] Intel-SIG: commit a9d0adc ("x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:e6dfdc2e89a0adedf455814c91b977d6a584cc88 severity: Moderate upstream commit e6dfdc2 ("x86/cpu/vfm: Add new macros to work with (vendor/family/model) values") To avoid adding a slew of new macros for each new Intel CPU family switch over from providing CPU model number #defines to a new scheme that encodes vendor, family, and model in a single number. [ bp: s/casted/cast/g ] Intel-SIG: commit e6dfdc2 ("x86/cpu/vfm: Add new macros to work with (vendor/family/model) values") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:f055b6260eb3ef20a6e310d1e555a5d5a0a28ca0 severity: Moderate upstream commit f055b62 ("x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h") New CPU #defines encode vendor and family as well as model. Update the example usage comment in arch/x86/kernel/cpu/match.c Intel-SIG: commit f055b62 ("x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:243218ca93037631f0224fdbefea045912cb761a severity: Moderate upstream commit 243218c ("perf/x86/intel/cstate: Cleanup duplicate attr_groups") The events of the cstate_core and cstate_pkg PMU have the same format. They both need to create a "events" group (with empty attrs). The attr_groups can be shared. Remove the dedicated attr_groups for each cstate PMU. Use the shared cstate_attr_groups to replace. Intel-SIG: commit 243218c ("perf/x86/intel/cstate: Cleanup duplicate attr_groups") Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:3877d55a0db2688c2e4ab8a319614a0c81f8e2d2 severity: Moderate upstream commit 3877d55 ("perf/x86/intel/cstate: Add Sierra Forest support") A new module C6 Residency Counter is introduced in the Sierra Forest. The scope of the new counter is module (A cluster of cores shared L2 cache). Create a brand new cstate_module PMU to profile the new counter. The only differences between the new cstate_module PMU and the existing cstate PMU are the scope and events. Regarding the choice of the new cstate_module PMU name, the current naming rule of a cstate PMU is "cstate_" + the scope of the PMU. The scope of the PMU is the cores shared L2. On SRF, Intel calls it "module", while the internal Linux sched code calls it "cluster". The "cstate_module" is used as the new PMU name, because - The Cstate PMU driver is a Intel specific driver. It doesn't impact other ARCHs. The name makes it consistent with the documentation. - The "cluster" mainly be used by the scheduler developer, while the user of cstate PMU is more likely a researcher reading HW docs and optimizing power. - In the Intel's SDM, the "cluster" has a different meaning/scope for topology. Using it will mislead the end users. Besides the module C6, the core C1/C6 and pkg C6 residency counters are supported in the Sierra Forest as well. Intel-SIG: commit 3877d55 ("perf/x86/intel/cstate: Add Sierra Forest support") Suggested-by: Artem Bityutskiy <[email protected]> Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:bbb968696d0f3442ab823598def3b756cf4735c6 severity: Moderate upstream commit bbb9686 ("perf/x86/intel/cstate: Add Grand Ridge support") The same as the Sierra Forest, the Grand Ridge supports core C1/C6 and module C6. But it doesn't support pkg C6 residency counter. Intel-SIG: commit bbb9686 ("perf/x86/intel/cstate: Add Grand Ridge support") Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:5ee800945a3466c3b126020c8f4ffc6b54d6986f severity: Moderate upstream commit 5ee8009 ("perf/x86/intel/cstate: Switch to new Intel CPU model defines") New CPU #defines encode vendor and family as well as model. Intel-SIG: commit 5ee8009 ("perf/x86/intel/cstate: Switch to new Intel CPU model defines") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Link: https://lore.kernel.org/all/20240424181459.41500-1-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:cf35791476fcb3230b98a42241a56242d60ebdd3 severity: Moderate upstream commit cf35791 ("perf/x86/intel/uncore: Generic uncore_get_uncores and MMIO format of SPR") Factor out SPR_UNCORE_MMIO_COMMON_FORMAT which can be reused by Granite Rapids in the following patch. Granite Rapids have more uncore units than Sapphire Rapids. Add new parameters to support adjustable uncore units. No functional change. Intel-SIG: commit cf35791 ("perf/x86/intel/uncore: Generic uncore_get_uncores and MMIO format of SPR") Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Tested-by: Ammy Yi <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:632c4bf6d007862307440b177d9fee829857e8bb severity: Moderate upstream commit 632c4bf ("perf/x86/intel/uncore: Support Granite Rapids") The same as Sapphire Rapids, Granite Rapids also supports the discovery table feature. All the basic uncore PMON information can be retrieved from the discovery table which resides in the BIOS. There are 4 new units are added on Granite Rapids, b2cmi, b2cxl, ubox, and mdf_sbo. The layout of the counters is exactly the same as the generic uncore counters. Only add a name for the new units. All the details can be retrieved from the discovery table. The description of the new units can be found at https://www.intel.com/content/www/us/en/secure/content-details/772943/content-details.html The other units, e.g., cha, iio, irp, pcu, and imc, are the same as Sapphire Rapids. Ignore the upi and b2upi units in the discovery table, which are broken for now. Intel-SIG: commit 632c4bf ("perf/x86/intel/uncore: Support Granite Rapids") Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Tested-by: Ammy Yi <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:cb4a6ccf35839895da63fcf6134d6fbd13224805 severity: Moderate upstream commit cb4a6cc ("perf/x86/intel/uncore: Support Sierra Forest and Grand Ridge") The same as Granite Rapids, the Sierra Forest and Grand Ridge also supports the discovery table feature and the same type of the uncore units. The difference of the available units and counters can be retrieved from the discovery table automatically. Just add the CPU model ID. Intel-SIG: commit cb4a6cc ("perf/x86/intel/uncore: Support Sierra Forest and Grand Ridge") Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Tested-by: Ammy Yi <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:9828a1cff456e0d6f55f9e148585313c2dd59c00 severity: Moderate upstream commit 9828a1c ("perf/x86/intel/uncore: Switch to new Intel CPU model defines") New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* uncore patches into one. ] Intel-SIG: commit 9828a1c ("perf/x86/intel/uncore: Switch to new Intel CPU model defines") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181501.41557-1-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
mainline:add69475de4b5196da9c58ba2d7c0182e70da2cb severity: Moderate upstream commit add6947 ("perf/x86/msr: Switch to new Intel CPU model defines") New CPU #defines encode vendor and family as well as model. Intel-SIG: commit add6947 ("perf/x86/msr: Switch to new Intel CPU model defines") Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/all/20240424181503.41614-1-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
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deepin pr auto reviewIntel: Fix SMP on older Intel processors Signed-off-by: Peter Sankauskas [email protected] |
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perf updates depends on x86 updates
x86 updates
f055b62,x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h,2024-04-22 11:44:00 +0200,Tony Luck [email protected],
e6dfdc2,x86/cpu/vfm: Add new macros to work with (vendor/family/model) values,2024-04-22 11:43:55 +0200,Tony Luck [email protected],
a9d0adc,x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86,2024-04-22 11:43:48 +0200,Tony Luck [email protected],
8a8a9c9,x86/cpu: Add model number for another Intel Arrow Lake mobile processor,2024-03-24 04:08:10 +0100,Tony Luck [email protected],v6.9
090e3be,x86/cpu: Add model number for Intel Clearwater Forest processor,2024-01-23 11:08:08 +0100,Tony Luck [email protected],v6.8
c3dd199,x86/smp: Export symbol cpu_clustergroup_mask(),2023-11-17 10:54:52 +0100,Kan Liang [email protected],v6.8
perf updates
add6947,perf/x86/msr: Switch to new Intel CPU model defines,2024-04-29 10:31:04 +0200,Tony Luck [email protected],
9828a1c,perf/x86/intel/uncore: Switch to new Intel CPU model defines,2024-04-29 10:30:39 +0200,Tony Luck [email protected],
cb4a6cc,perf/x86/intel/uncore: Support Sierra Forest and Grand Ridge,2023-11-24 20:25:03 +0100,Kan Liang [email protected],v6.8
632c4bf,perf/x86/intel/uncore: Support Granite Rapids,2023-11-24 20:25:01 +0100,Kan Liang [email protected],v6.8
cf35791,perf/x86/intel/uncore: Generic uncore_get_uncores and MMIO format of SPR,2023-11-24 20:25:00 +0100,Kan Liang [email protected],v6.8
5ee8009,perf/x86/intel/cstate: Switch to new Intel CPU model defines,2024-04-25 09:04:32 -0700,Tony Luck [email protected],
bbb9686,perf/x86/intel/cstate: Add Grand Ridge support,2023-11-17 10:54:53 +0100,Kan Liang [email protected],v6.8
3877d55,perf/x86/intel/cstate: Add Sierra Forest support,2023-11-17 10:54:53 +0100,Kan Liang [email protected],v6.8
243218c,perf/x86/intel/cstate: Cleanup duplicate attr_groups,2023-11-17 10:54:52 +0100,Kan Liang [email protected],v6.8