LoongArch: fix some pci problems（Pull request again） #192
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added 9 commits
May 23, 2024 14:43
Signed-off-by: Baoqi Zhang <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
Fix patch "LoongArch: Add PCI controller support" Signed-off-by: Tianli Xiong <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
…ccess configuration space Fix patch "PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A" Signed-off-by: Tianli Xiong <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
Don't limit mrrs during resume, so that saved value can be restored. Fix patch "PCI: loongson: Improve the MRRS quirk for LS7A" Signed-off-by: Jianmin Lv <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
fix kabi error caused by pm_suspend_target_state,used only by loongson devices. Signed-off-by: Hongchen Zhang <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
Fix some pcie card not scanning properly when bus number is inconsistent during firmware and kernel scan phases. Signed-off-by: liuyun <[email protected]> Signed-off-by: Tianli Xiong <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
Signed-off-by: Jianmin Lv <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
Add window to solve GPU access error Signed-off-by: Baoqi Zhang <[email protected]> Signed-off-by: Yanteng Si <[email protected]>
According to PCI-to-PCI bridge spec, bit 3 of Bridge Control Register
is VGA Enable bit which modifies the response by the bridge to VGA
compatible addresses.
The Bridge Control register provides extensions to the Command register
that are specific to a bridge. The Bridge Control register provides
many of the same controls for the secondary interface that are provided
by the Command register for the primary interface. There are some bits
that affect the operation of both interfaces of the bridge.
If the VGA Enable bit is set, the bridge will positively decode
and forward the following accesses on the primary interface to
the secondary interface (and, conversely, block the forwarding
of these addresses from the secondary to primary interface)
Forwarding of these accesses is qualified by the I/O Enable and
Memory Enable bits in the Command register.) The default state of
this bit after reset must be 0.
Bit 3 of Bridge Control Register is VGA Enable bit which modifies the
response by the bridge to VGA compatible addresses.
when 0: do not forward VGA compatible memory and I/O addresses from
the primary to secondary interface (addresses defined below)
unless they are enabled for forwarding by the defined I/O
when 1: forward VGA compatible memory and I/O addresses (addresses
defined below) from the primary interface to the secondary
interface (if the I/O Enable and Memory Enable bits are set)
independent of the I/O and memory address ranges and
independent of the ISA Enable bit
* memory accesses in the range 000A 0000h to 000B FFFFh
* I/O addresses in the first 64 KB of the I/O address space
(AD[31:16] are 0000h) where AD[9:: 0] are in the ranges
3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address
aliases - AD[15::10] are not decoded)
If the VGA Enable bit is set, forwarding of these accesses is
independent of the I/O address range and memory address ranges
defined by the I/O Base and Limit registers, the Memory Base
and Limit registers, and the Prefetchable Memory Base and Limit
registers of the bridge.
Forwarding of these accesses is also independent of the settings
of the ISA Enable bit (in the Bridge Control register) or VGA
Palette Snoop bits (in the Command register).
The AST2500 hardware we are using do not set the VGA Enable bit on
its bridge control reg, this cause vgaarb subsystem don't think the
VGA card behind this pridge as a valid boot vga device which made
X server choose wrong video card to use when multiple video card
present in the system.
Its seems more vgaarb's fault than the ast2500 bmc itself.
even through bit 3 of Bridge Control Register is 0, it should still
allow to forward the accesses when the addresses is in the range of
IO/MEM Base and Limit registers.
Nevertheless, in order to support loongson CPU product line, we
provide a workaround to this bug for the Sugon L620-G30 and Sugon
L820-G30 server.
see similar bug:
https://patchwork.kernel.org/project/linux-pci/patch/[email protected]/
Signed-off-by: suijingfeng <[email protected]>
Signed-off-by: Yanteng Si <[email protected]>
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Hi @sterling-teng. Thanks for your PR. I'm waiting for a deepin-community member to verify that this patch is reasonable to test. If it is, they should reply with Once the patch is verified, the new status will be reflected by the I understand the commands that are listed here. Instructions for interacting with me using PR comments are available here. If you have questions or suggestions related to my behavior, please file an issue against the kubernetes/test-infra repository. |
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/ok-to-test |
deepin pr auto review关键摘要:
是否建议立即修改:
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Avenger-285714
merged commit d80b4ae
into
deepin-community:linux-6.6.y
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