Edac: Add Phytium edac controller support

Documentation/devicetree/bindings/edac/phytium,pe220x-edac.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/phytium,pe220x-edac.yaml
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium Pe220x SoC EDAC node
+maintainers:
+  - Zhu Honglei <[email protected]>
+
+description: |
+        EDAC node is defined to describe on-chip error detection and correction.
+
+properties:
+  compatible:
+    const: phytium,pe220x-edac
+
+  reg:
+    maxItems: 3
+
+  interrupts:
+    minItems: 2
+    items:
+      - description: Interrupt-specifier for RAS error IRQ(s).
+
+required:
+  - compatible: Shall be "phytium,pe220x-edac".
+  - reg: Shall be the Pe220x RAS resource.
+  - interrupts: Interrupt-specifier for RAS error IRQ(s).
+
+examples:
+  - |
+	edac: edac@32b28000 {
+		compatible = "phytium,pe220x-edac";
+		reg = <0x0 0x32b28000 0x0 0x1000>,
+			<0x0 0x31400000 0x0 0x1000>,
+			<0x0 0x31401000 0x0 0x1000>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+	};

drivers/edac/Kconfig

@@ -515,6 +515,13 @@ config EDAC_TI
 	help
 	  Support for error detection and correction on the TI SoCs.
 
+config EDAC_PHYTIUM
+	tristate "Phytium Pe220x SoC"
+	depends on (ARM64)
+	help
+	  Support for error detection and correction on the
+	  Phytium Pe220x family of SOCs.
+
 config EDAC_QCOM
 	tristate "QCOM EDAC Controller"
 	depends on ARCH_QCOM && QCOM_LLCC

drivers/edac/Makefile

@@ -81,6 +81,7 @@ obj-$(CONFIG_EDAC_ARMADA_XP)		+= armada_xp_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
 obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
+obj-$(CONFIG_EDAC_PHYTIUM)		+= phytium_edac.o
 obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
 obj-$(CONFIG_EDAC_ASPEED)		+= aspeed_edac.o
 obj-$(CONFIG_EDAC_BLUEFIELD)		+= bluefield_edac.o