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drm/arise: Upgrade Glenfly Arise driver to 25.00.36
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Signed-off-by: WangYuli <[email protected]>
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@Avenger-285714
Avenger-285714 committed Nov 24, 2024
1 parent f658001 commit eaaaf30
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Showing 22 changed files with 537 additions and 70 deletions.
3 changes: 3 additions & 0 deletions drivers/gpu/drm/arise/cbios/CBios.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2623,6 +2623,9 @@ CBiosDDCCII2CAccess(CBIOS_VOID* pcbe, PCBIOS_I2CCONTROL pI2CControl, CBIOS_UCHAR
DLLEXPORTS CBIOS_STATUS
CBiosSetIgaScreenOnOffState(CBIOS_VOID* pcbe, CBIOS_S32 status, CBIOS_UCHAR IGAIndex);

DLLEXPORTS CBIOS_STATUS
CBiosSetIgaOnOffState(CBIOS_VOID* pcbe, CBIOS_S32 status, CBIOS_UCHAR IGAIndex);

DLLEXPORTS CBIOS_STATUS
CBiosSetDisplayDevicePowerState(CBIOS_VOID* pcbe, CBIOS_U32 DevicesId, CBIOS_PM_STATUS PMState);

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21 changes: 21 additions & 0 deletions drivers/gpu/drm/arise/cbios/Device/CBiosChipShare.h
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Original file line number Diff line number Diff line change
Expand Up @@ -256,6 +256,27 @@ typedef struct _CBIOS_EXTENSION_COMMON

} CBIOS_EXTENSION_COMMON, *PCBIOS_EXTENSION_COMMON;

typedef union _GPIO_REGISTER
{
CBIOS_U16 Value;
struct
{
CBIOS_U16 GPIO_Enable :1;
CBIOS_U16 GPIO_SL :1;
CBIOS_U16 GPIO_DS2 :1;
CBIOS_U16 GPIO_DS1 :1;
CBIOS_U16 GPIO_DS0 :1;
CBIOS_U16 GPIO_PD :1;
CBIOS_U16 GPIO_PU :1;
CBIOS_U16 GPIO_ST :1;
CBIOS_U16 GPIO_OE :1; //Output Enable
CBIOS_U16 GPIO_OUT :1; //Output Data
CBIOS_U16 GPIO_IE :1; //Input Enable
CBIOS_U16 IP_SL_1 :1;
CBIOS_U16 GPIO_Data_In :1; //Input Data
CBIOS_U16 Reserved :3;
};
}GPIO_REGISTER;

//************************* CBios sw utility functions ***************************//
CBIOS_BOOL cbCalcCustomizedTiming(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_U32 XRes, CBIOS_U32 YRes, CBIOS_U32 RefreshRate, PCBIOS_TIMING_ATTRIB pTimingReg);
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8 changes: 4 additions & 4 deletions drivers/gpu/drm/arise/cbios/Device/CBiosDeviceShare.c
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Original file line number Diff line number Diff line change
Expand Up @@ -572,7 +572,7 @@ CBIOS_MONITOR_TYPE cbGetSupportMonitorType(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE
}
else
{
MonitorType |= CBIOS_MONITOR_TYPE_CRT | CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
MonitorType |= CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
}
}

Expand All @@ -584,7 +584,7 @@ CBIOS_MONITOR_TYPE cbGetSupportMonitorType(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE
}
else
{
MonitorType |= CBIOS_MONITOR_TYPE_CRT | CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
MonitorType |= CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
}
}

Expand All @@ -596,7 +596,7 @@ CBIOS_MONITOR_TYPE cbGetSupportMonitorType(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE
}
else
{
MonitorType |= CBIOS_MONITOR_TYPE_CRT | CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
MonitorType |= CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
}
}

Expand All @@ -608,7 +608,7 @@ CBIOS_MONITOR_TYPE cbGetSupportMonitorType(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE
}
else
{
MonitorType |= CBIOS_MONITOR_TYPE_CRT | CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
MonitorType |= CBIOS_MONITOR_TYPE_DP | CBIOS_MONITOR_TYPE_DVI | CBIOS_MONITOR_TYPE_HDMI;
}
}

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29 changes: 1 addition & 28 deletions drivers/gpu/drm/arise/cbios/Device/gcc_stdarg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -13,17 +13,6 @@
//*****************************************************************************


/* As a special exception, if you include this header file into source
files compiled by GCC, this header file does not by itself cause
the resulting executable to be covered by the GNU General Public
License. This exception does not however invalidate any other
reasons why the executable file might be covered by the GNU General
Public License. */

/*
* ISO C Standard: 7.15 Variable arguments <stdarg.h>
*/

#ifndef _STDARG_H
#ifndef _ANSI_STDARG_H_
#ifndef __need___va_list
Expand All @@ -32,8 +21,6 @@
#endif /* not __need___va_list */
#undef __need___va_list

/* Define __gnuc_va_list. */

#ifndef __GNUC_VA_LIST
#define __GNUC_VA_LIST
typedef __builtin_va_list __gnuc_va_list;
Expand All @@ -51,13 +38,6 @@ typedef __builtin_va_list __gnuc_va_list;
#endif
#define __va_copy(d,s) __builtin_va_copy(d,s)

/* Define va_list, if desired, from __gnuc_va_list. */
/* We deliberately do not define va_list when called from
stdio.h, because ANSI C says that stdio.h is not supposed to define
va_list. stdio.h needs to have access to that data type,
but must not use that name. It should use the name __gnuc_va_list,
which is safe because it is reserved for the implementation. */

#ifdef _HIDDEN_VA_LIST /* On OSF1, this means varargs.h is "half-loaded". */
#undef _VA_LIST
#endif
Expand All @@ -67,10 +47,7 @@ typedef __builtin_va_list __gnuc_va_list;
#endif

#if defined(__svr4__) || (defined(_SCO_DS) && !defined(__VA_LIST))
/* SVR4.2 uses _VA_LIST for an internal alias for va_list,
so we must avoid testing it and setting it here.
SVR4 uses _VA_LIST as a flag in stdarg.h, but we should
have no conflict with that. */

#ifndef _VA_LIST_
#define _VA_LIST_
#ifdef __i860__
Expand All @@ -85,10 +62,6 @@ typedef __gnuc_va_list va_list;
#endif /* _VA_LIST_ */
#else /* not __svr4__ || _SCO_DS */

/* The macro _VA_LIST_ is the same thing used by this file in Ultrix.
But on BSD NET2 we must not test or define or undef it.
(Note that the comments in NET 2's ansi.h
are incorrect for _VA_LIST_--see stdio.h!) */
#if !defined (_VA_LIST_) || defined (__BSD_NET2__) || defined (____386BSD____) || defined (__bsdi__) || defined (__sequent__) || defined (__FreeBSD__) || defined(WINNT)
/* The macro _VA_LIST_DEFINED is used in Windows NT 3.5 */
#ifndef _VA_LIST_DEFINED
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78 changes: 78 additions & 0 deletions drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_CRT.c
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Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@ CBIOS_VOID cbDIU_CRT_SetHVSync(PCBIOS_VOID pvcbe, CBIOS_U8 HVPolarity, CBIOS_U8
PCBIOS_EXTENSION_COMMON pcbe = (PCBIOS_EXTENSION_COMMON)pvcbe;
CBIOS_ACTIVE_TYPE DevicePort = 0;
CBIOS_U8 byTemp = 0;
GPIO_REGISTER Gpio21Value;

DevicePort = pcbe->DispMgr.ActiveDevices[IGAIndex];

Expand Down Expand Up @@ -90,6 +91,23 @@ CBIOS_VOID cbDIU_CRT_SetHVSync(PCBIOS_VOID pvcbe, CBIOS_U8 HVPolarity, CBIOS_U8
{
cbMMIOWriteReg(pcbe, CR_55, (byTemp >> 6), 0xFC);
}

if (pcbe->ChipID == CHIPID_ARISE2030)
{
// Set GPIO21 for Blue pin
Gpio21Value.Value = 0;
Gpio21Value.GPIO_OE = 1;
if (HVPolarity & VerNEGATIVE)
{
Gpio21Value.GPIO_OUT = 1; // if VerNEGATIVE, output = 1
}
else
{
Gpio21Value.GPIO_OUT = 0; // if VerPOSITIVE, output = 0
}
cb_WriteU16(pcbe->pAdapterContext, 0xA005C, Gpio21Value.Value); // GPIO21 = 0xA0058, swap 58 --> 5C
}

}
}

Expand Down Expand Up @@ -251,6 +269,61 @@ static CBIOS_BOOL cbIsNeedDacSense(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_DAC_SENS
return bNeedSense;
}

CBIOS_BOOL cbArise2030_DACSense(PCBIOS_VOID pvcbe, PCBIOS_DEVICE_COMMON pDevCommon)
{
PCBIOS_EXTENSION_COMMON pcbe = (PCBIOS_EXTENSION_COMMON)pvcbe;
CBIOS_U32 IGAIndex = pDevCommon->DispSource.ModuleList.IGAModule.Index;
CBIOS_BOOL bStatus = CBIOS_FALSE;
GPIO_REGISTER Gpio21Value, Gpio22Value;

if(pDevCommon->PowerState != CBIOS_PM_ON)
{
// Set GPIO21
Gpio21Value.Value = 0;
Gpio21Value.GPIO_OE = 1;
Gpio21Value.GPIO_OUT = 0;
cb_WriteU16(pcbe->pAdapterContext, 0xA005C, Gpio21Value.Value); // GPIO21 = 0xA0058, swap 58 --> 5C
cb_DelayMicroSeconds(200);//delay 200us
Gpio21Value.Value = 0;
Gpio21Value.GPIO_OE = 1;
Gpio21Value.GPIO_OUT = 1;
cb_WriteU16(pcbe->pAdapterContext, 0xA005C, Gpio21Value.Value); //swap 58 --> 5C
cb_DelayMicroSeconds(200);//delay 200us
Gpio21Value.Value = 0;
Gpio21Value.GPIO_OE = 1;
Gpio21Value.GPIO_OUT = 0;
cb_WriteU16(pcbe->pAdapterContext, 0xA005C, Gpio21Value.Value); //swap 58 --> 5C

// Set GPIO22 Input Enable
Gpio22Value.Value = 0;
Gpio22Value.GPIO_IE = 1;
cb_WriteU16(pcbe->pAdapterContext, 0xA0058, Gpio22Value.Value); // GPIO22 = 0xA005C, swap 5C --> 58
cb_DelayMicroSeconds(200);//delay 200us

// Read GPIO22 Input Value
Gpio22Value.Value = cb_ReadU16(pcbe->pAdapterContext, 0xA0058); // GPIO22 = 0xA005C, swap 5C --> 58
if(Gpio22Value.GPIO_Data_In == 0) // 0: connect; 1: not connect
{
bStatus = CBIOS_TRUE;
}
}
else
{
// Set GPIO22 Input Enable
Gpio22Value.Value = 0;
Gpio22Value.GPIO_IE = 1;
cb_WriteU16(pcbe->pAdapterContext, 0xA0058, Gpio22Value.Value); // GPIO22 = 0xA005C, swap 5C --> 58
cbWaitVSync(pcbe, (CBIOS_U8)IGAIndex);

// Read GPIO22 Input Value
Gpio22Value.Value = cb_ReadU16(pcbe->pAdapterContext, 0xA0058); // GPIO22 = 0xA005C, swap 5C --> 58
if(Gpio22Value.GPIO_Data_In == 0) // 0: connect; 1: not connect
{
bStatus = CBIOS_TRUE;
}
}
return bStatus;
}
CBIOS_BOOL cbDIU_CRT_DACSense(PCBIOS_VOID pvcbe, PCBIOS_DEVICE_COMMON pDevCommon, CBIOS_BOOL bPrevEdidValid)
{
PCBIOS_EXTENSION_COMMON pcbe = (PCBIOS_EXTENSION_COMMON)pvcbe;
Expand All @@ -263,6 +336,11 @@ CBIOS_BOOL cbDIU_CRT_DACSense(PCBIOS_VOID pvcbe, PCBIOS_DEVICE_COMMON pDevCommon
REG_CR71_Pair RegCR71Value, RegCR71Mask;
CBIOS_DAC_SENSE_PARA DacSensePara = {0};

if (pcbe->ChipID == CHIPID_ARISE2030)
{
return cbArise2030_DACSense(pcbe, pDevCommon);
}

DacSensePara.PowerState = pDevCommon->PowerState;
DacSensePara.PrevEdidValid = (bPrevEdidValid)? 1 : 0;

Expand Down
28 changes: 23 additions & 5 deletions drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosPHY_DP.c
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Original file line number Diff line number Diff line change
Expand Up @@ -236,6 +236,7 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule
REG_MM334E0 DPEphySetting1RegValue, DPEphySetting1RegMask;
REG_MM836C DPEphyStatusRegValue, DPEphyStatusRegMask;
REG_MM334E4 DPEphySetting2RegValue, DPEphySetting2RegMask;
CBIOS_BOOL bACE = ((pcbe->ChipID == CHIPID_ARISE2030) || (pcbe->ChipID == CHIPID_ARISE2020)) ? CBIOS_TRUE : CBIOS_FALSE;

cbTraceEnter(DP);

Expand Down Expand Up @@ -370,7 +371,7 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule

DPEphyStatusRegValue.Value = 0;
DPEphyStatusRegValue.EPHY1_TPLL_ISEL = 0;
if (ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T))
if ((ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T)) || (ClockFreq < 3400000 && bACE))
{
DPEphyStatusRegValue.TR = 0;
DPEphyStatusRegValue.TC = 7;
Expand Down Expand Up @@ -403,7 +404,7 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule
}
else
{
DPEphySetting1RegValue.EPHY1_FBOOST = 1;
DPEphySetting1RegValue.EPHY1_FBOOST = bACE ? 2 : 1;
}
}
else if(ClockFreq >= 1700000)
Expand Down Expand Up @@ -584,11 +585,28 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule
}
else
{
if(bACE)
{
DPSwingRegValue.Value = 0;
DPSwingRegValue.enable_SW_swing_pp = 1;
DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 9;
DPSwingRegValue.DP1_SW_swing = 0x2E;
DPSwingRegValue.DP1_SW_pp = 0x9;
DPSwingRegValue.DP1_SW_post_cursor = 0;

DPSwingRegMask.Value = 0xFFFFFFFF;
DPSwingRegMask.enable_SW_swing_pp = 0;
DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0;
DPSwingRegMask.DP1_SW_swing = 0;
DPSwingRegMask.DP1_SW_pp = 0;
DPSwingRegMask.DP1_SW_post_cursor = 0;
cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value);
}
DPSwingRegValue.Value = 0;
DPSwingRegValue.enable_SW_swing_pp = 1;
DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 1;
DPSwingRegValue.DP1_SW_swing = 0x3F;
DPSwingRegValue.DP1_SW_pp = 0x18;
DPSwingRegValue.DP1_SW_swing = bACE ? 0x36 : 0x3F;
DPSwingRegValue.DP1_SW_pp = bACE ? 0x1A : 0x18;
DPSwingRegValue.DP1_SW_post_cursor = 0;

DPSwingRegMask.Value = 0xFFFFFFFF;
Expand Down Expand Up @@ -623,7 +641,7 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule
DPLinkRegValue.SW_Link_Train_State = 1;
DPLinkRegValue.Software_Bit_Rate = 0;
DPLinkRegValue.SW_Lane0_Swing = 0;
DPLinkRegValue.SW_Lane0_Pre_emphasis = 0;
DPLinkRegValue.SW_Lane0_Pre_emphasis = bACE ? 2 : 0;
DPLinkRegValue.SW_Lane1_Swing = 0;
DPLinkRegValue.SW_Lane1_Pre_emphasis = 0;
DPLinkRegValue.SW_Lane2_Swing = 0;
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/arise/cbios/Hw/HwCallback/CBiosCallbacksHw.h
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ typedef CBIOS_VOID (*CALLBACK_cbRegulatorPut)(PCBIOS_VOID Regulator);


CBIOS_UCHAR cb_ReadU8(PCBIOS_VOID pAdapterContext, CBIOS_U32 RegisterPort);
CBIOS_U16 cb_cbReadU16(PCBIOS_VOID pAdapterContext, CBIOS_U32 RegisterPort);
CBIOS_U16 cb_ReadU16(PCBIOS_VOID pAdapterContext, CBIOS_U32 RegisterPort);
CBIOS_U32 cb_ReadU32(PCBIOS_VOID pAdapterContext, CBIOS_U32 RegisterPort);

CBIOS_VOID cb_WriteU8(PCBIOS_VOID pAdapterContext, CBIOS_U32 RegisterPort, CBIOS_UCHAR Value);
Expand Down
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