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Merge pull request #258 from leoliu-oc/linux-6.6.y-17-padlock
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[linux-6.6.y] Driver for Zhaoxin AES and SHA algorithm
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opsiff authored Jun 19, 2024
2 parents bd2edcf + 6ec9972 commit ab5b147
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Showing 6 changed files with 873 additions and 2 deletions.
42 changes: 42 additions & 0 deletions drivers/crypto/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -52,6 +52,48 @@ config CRYPTO_DEV_PADLOCK_SHA
If unsure say M. The compiled module will be
called padlock-sha.

config CRYPTO_DEV_ZHAOXIN
tristate "Support for Zhaoxin ACE"
depends on X86 && !UML
default m
help
Some Zhaoxin processors come with an integrated crypto engine
(so called Zhaoxin ACE, Advanced Cryptography Engine)
that provides instructions for very fast cryptographic
operations with supported algorithms.

The instructions are used only when the CPU supports them.
Otherwise software encryption is used.

config CRYPTO_DEV_ZHAOXIN_AES
tristate "Zhaoxin ACE driver for AES algorithm"
depends on CRYPTO_DEV_ZHAOXIN
default CRYPTO_DEV_ZHAOXIN
select CRYPTO_BLKCIPHER
select CRYPTO_AES
help
Use Zhaoxin ACE for AES algorithm.

Available in Zhaoxin CPUs.

If unsure say M. The compiled module will be
called zhaoxin-aes.

config CRYPTO_DEV_ZHAOXIN_SHA
tristate "Zhaoxin ACE driver for SHA1 and SHA256 algorithms"
depends on CRYPTO_DEV_ZHAOXIN
default CRYPTO_DEV_ZHAOXIN
select CRYPTO_HASH
select CRYPTO_SHA1
select CRYPTO_SHA256
help
Use Zhaoxin ACE for SHA1/SHA256 algorithms.

Available in Zhaoxin processors.

If unsure say M. The compiled module will be
called zhaoxin-sha.

config CRYPTO_DEV_GEODE
tristate "Support for the Geode LX AES engine"
depends on X86_32 && PCI
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2 changes: 2 additions & 0 deletions drivers/crypto/Makefile
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Expand Up @@ -31,6 +31,8 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o
obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
obj-$(CONFIG_CRYPTO_DEV_ZHAOXIN_AES) += zhaoxin-aes.o
obj-$(CONFIG_CRYPTO_DEV_ZHAOXIN_SHA) += zhaoxin-sha.o
obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o
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2 changes: 1 addition & 1 deletion drivers/crypto/padlock-aes.c
Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,7 @@ static struct skcipher_alg cbc_aes_alg = {
};

static const struct x86_cpu_id padlock_cpu_id[] = {
X86_MATCH_FEATURE(X86_FEATURE_XCRYPT, NULL),
{ X86_VENDOR_CENTAUR, 6, X86_MODEL_ANY, X86_FEATURE_XCRYPT },
{}
};
MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);
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2 changes: 1 addition & 1 deletion drivers/crypto/padlock-sha.c
Original file line number Diff line number Diff line change
Expand Up @@ -491,7 +491,7 @@ static struct shash_alg sha256_alg_nano = {
};

static const struct x86_cpu_id padlock_sha_ids[] = {
X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL),
{ X86_VENDOR_CENTAUR, 6, X86_MODEL_ANY, X86_FEATURE_PHE },
{}
};
MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
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