irqchip/irq-gic-v3-its: Enable nonboot CPUs LPIS when resume from S3

When system resume from suspend to ram, firmware just restore GICR_CTLR_ENABLE_LPIs of boot CPU, the other CPUs also should be restored. Signed-off-by: Li Yuting <[email protected]> Signed-off-by: Wang Xu <[email protected]> Signed-off-by: Feng Jun <[email protected]> Signed-off-by: Chen Baozi <[email protected]> Signed-off-by: Wang Yinfeng <[email protected]>
deepin-community · May 20, 2024 · 9c8d79c · 9c8d79c
1 parent 9e5464d
commit 9c8d79c
Showing 1 changed file with 18 additions and 0 deletions.
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
@@ -4888,6 +4888,7 @@ static void its_restore_enable(void)
 {
 	struct its_node *its;
 	int ret;
+	int cpu;
 
 	raw_spin_lock(&its_lock);
 	list_for_each_entry(its, &its_nodes, entry) {
@@ -4941,6 +4942,23 @@ static void its_restore_enable(void)
 		    GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
 			its_cpu_init_collection(its);
 	}
+
+	/*
+	 * Enable LPIs:firmware just restore GICR_CTLR_ENABLE_LPIs of boot
+	 * CPU, the other CPUs also should be restored.
+	 */
+	for_each_possible_cpu(cpu) {
+		void __iomem *rbase = gic_data_rdist_cpu(cpu)->rd_base;
+		u32 val;
+
+		/* Enable LPIs */
+		val = readl_relaxed(rbase + GICR_CTLR);
+		if (val & GICR_CTLR_ENABLE_LPIS)
+			continue;
+
+		val |= GICR_CTLR_ENABLE_LPIS;
+		writel_relaxed(val, rbase + GICR_CTLR);
+	}
 	raw_spin_unlock(&its_lock);
 }