fix timing violation in RX datapath and add support for blue-crc updates

fpga/UdpCmacLoopPerfTest/Makefile

@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
 SCRIPTS_DIR = $(ROOT_DIR)/scripts
 include $(SCRIPTS_DIR)/Makefile.base
 LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
-LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
-CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
+LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
+LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
+CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
 BSV_DIR = ../common/bsv
 
 # Design Configurations
@@ -61,6 +62,10 @@ endif
 
 verilog: $(BSV_MODULES)
 	cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
+ifeq ($(SUPPORT_RDMA), True)
+	find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
+endif
+
 $(BSV_MODULES):
 	mkdir -p $(BUILDDIR)
 	mkdir -p $(DIR_VLOG_GEN)

fpga/UdpCmacPerfTest/Makefile

@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
 SCRIPTS_DIR = $(ROOT_DIR)/scripts
 include $(SCRIPTS_DIR)/Makefile.base
 LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
-LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
-CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
+LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
+LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
+CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
 BSV_DIR = ../common/bsv
 
 # Design Configurations
@@ -62,6 +63,10 @@ endif
 
 verilog: $(BSV_MODULES)
 	cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
+ifeq ($(SUPPORT_RDMA), True)
+	find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
+endif
+
 $(BSV_MODULES):
 	mkdir -p $(BUILDDIR)
 	mkdir -p $(DIR_VLOG_GEN)

fpga/XdmaUdpCmac/Makefile

@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
 SCRIPTS_DIR = $(ROOT_DIR)/scripts
 include $(SCRIPTS_DIR)/Makefile.base
 LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
-LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
-CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
+LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
+LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
+CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
 BSV_DIR = ../common/bsv
 
 # Design Configurations
@@ -13,15 +14,15 @@ BSV_DIR = ../common/bsv
 # SUPPORT_RDMA: False - Disable, True - Enable
 QSFP_IDX = 1
 ENABLE_CMAC_RSFEC = 1
-#ENABLE_ARP_PROCESS = 0
+ENABLE_BYPASS_MODE = 1
 ENABLE_DEBUG_MODE = 1
-SUPPORT_RDMA ?= False
+SUPPORT_RDMA ?= True
 
 MACROFLAGS = -D IS_SUPPORT_RDMA=$(SUPPORT_RDMA)
 
 # Pass arguments to vivado
 export PART = xcvu13p-fhgb2104-2-i
-export BUILD_TOP = XdmaUdpCmacWrapper
+export BUILD_TOP = XdmaUdpCmacWrapper512
 
 ## Directories and Files
 export DIR_VLOG = ./verilog
@@ -45,7 +46,7 @@ export DEBUG_PROBES_EN = 1
 export TARGET_CLOCKS = xdma_axi_aclk
 export MAX_NET_PATH_NUM = 1000
 
-BSV_MODULES = CmacRecvMonitor CmacSendMonitor XdmaUdpIpEthCmacRxTx
+BSV_MODULES = CmacRecvMonitor CmacSendMonitor XdmaUdpIpEthCmacRxTx XdmaUdpIpEthBypassCmacRxTx
 IP = xdma clk_wiz cmac_mon_ila axis512_mon_ila
 ifeq ($(ENABLE_CMAC_RSFEC), 1)
 IP += cmac_rsfec_q$(QSFP_IDX)
@@ -55,19 +56,24 @@ endif
 XDC = common pciex16 qsfp$(QSFP_IDX)
 
 
-table:
+mem_init:
 ifeq ($(SUPPORT_RDMA), True)
+	mkdir -p $(DIR_MEM_CONFIG)
 	python3 $(CRC_TAB_SCRIPT) $(SCRIPTS_DIR)/crc_ieee_32_1024.json $(DIR_MEM_CONFIG)
 endif
 
 verilog: $(BSV_MODULES)
 	cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
+ifeq ($(SUPPORT_RDMA), True)
+	find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
+endif
 $(BSV_MODULES):
 	mkdir -p $(BUILDDIR)
 	mkdir -p $(DIR_VLOG_GEN)
 	bsc -elab $(VERILOGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(TRANSFLAGS) $(MACROFLAGS) -g mk$@ $(BSV_DIR)/$@.bsv
 	bluetcl $(SCRIPTS_DIR)/listVlogFiles.tcl -bdir $(BUILDDIR) -vdir $(BUILDDIR) mk$@ mk$@ | grep -i '\.v' | xargs -I {} cp {} $(DIR_VLOG_GEN)
 
+
 ip: $(IP)
 $(IP):
 	@mkdir -p $(DIR_IP_TCL)
@@ -87,8 +93,11 @@ endif
 ifeq ($(ENABLE_DEBUG_MODE), 1)
 	@echo "\`define ENABLE_DEBUG_MODE" >> $(CONFIG_FILE)
 endif
+ifeq ($(ENABLE_BYPASS_MODE), 1)
+	@echo "\`define ENABLE_BYPASS_MODE" >> $(CONFIG_FILE)
+endif
 
-build: table verilog ip xdc config
+build: mem_init verilog ip xdc config
 	vivado -mode batch -source ../common/tcl/non_proj_build.tcl 2>&1 | tee ./build_run.log
 
 clean:

fpga/XdmaUdpCmac/verilog/XdmaUdpCmacWrapper.v

@@ -1,5 +1,5 @@
 
-module XdmaUdpCmacWrapper#(
+module XdmaUdpCmacWrapper256#(
     parameter PCIE_GT_LANE_WIDTH = 16,
     parameter CMAC_GT_LANE_WIDTH = 4
 )(
@@ -419,8 +419,8 @@ module XdmaUdpCmacWrapper512#(
         .xdma_clk  (xdma_axi_aclk   ),
         .xdma_reset(xdma_axi_aresetn),
 
-        .udp_clk   (udp_clk  ),
-        .udp_reset (udp_reset),
+        .udp_clk   (xdma_axi_aclk   ),
+        .udp_reset (xdma_axi_aresetn),
 
         .gt_ref_clk_p(qsfp_ref_clk_p    ),
         .gt_ref_clk_n(qsfp_ref_clk_n    ),

fpga/XdmaUdpCmacLoop/Makefile

@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
 SCRIPTS_DIR = $(ROOT_DIR)/scripts
 include $(SCRIPTS_DIR)/Makefile.base
 LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
-LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
-CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
+LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
+LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
+CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
 BSV_DIR = ../common/bsv
 
 # Design Configurations
@@ -61,6 +62,10 @@ endif
 
 verilog: $(BSV_MODULES)
 	cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
+ifeq ($(SUPPORT_RDMA), True)
+	find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
+endif
+
 $(BSV_MODULES):
 	mkdir -p $(BUILDDIR)
 	mkdir -p $(DIR_VLOG_GEN)

fpga/XdmaUdpCmacPerfTest/Makefile

@@ -2,8 +2,9 @@ ROOT_DIR = $(abspath ../../)
 SCRIPTS_DIR = $(ROOT_DIR)/scripts
 include $(SCRIPTS_DIR)/Makefile.base
 LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
-LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(ROOT_DIR)/lib/blue-crc/src
-CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
+LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc
+LIBSRCDIR = $(ROOT_DIR)/lib/blue-wrapper/src:$(LIB_CRC_DIR)/src
+CRC_TAB_SCRIPT = $(LIB_CRC_DIR)/scripts/gen_crc_tab.py
 BSV_DIR = ../common/bsv
 
 # Design Configurations
@@ -64,6 +65,10 @@ endif
 
 verilog: $(BSV_MODULES)
 	cp ../common/verilog/UdpCmacRxTxWrapper.v $(DIR_VLOG_GEN)
+ifeq ($(SUPPORT_RDMA), True)
+	find $(LIB_CRC_DIR)/lib/primitives/ -name "*.v" -exec cp {} $(DIR_VLOG_GEN) \;
+endif
+
 $(BSV_MODULES):
 	mkdir -p $(BUILDDIR)
 	mkdir -p $(DIR_VLOG_GEN)

fpga/common/bsv/TestUdpCmacRxTx.bsv

@@ -13,7 +13,7 @@ import AxiStreamTypes :: *;
 typedef 33 CYCLE_COUNT_WIDTH;
 typedef 16 CASE_COUNT_WIDTH;
 typedef  8 FRAME_COUNT_WIDTH;
-typedef 256 TEST_CASE_NUM;
+typedef  4 TEST_CASE_NUM;
 
 typedef 2048 PAYLOAD_BYTE_NUM;
 typedef TMul#(PAYLOAD_BYTE_NUM, 8) PAYLOAD_WIDTH;
@@ -55,7 +55,7 @@ module mkTestUdpCmacRxTx(TestUdpCmacRxTx);
 
 
     // Input/Output FIFO
-    FIFOF#(AxiStream512) refAxiStreamBuf <- mkSizedFIFOF(valueOf(TEST_CASE_NUM));
+    FIFOF#(AxiStream512) refAxiStreamBuf <- mkSizedFIFOF(512);
     FIFOF#(AxiStream512) xdmaAxiStreamOutTxBuf <- mkFIFOF;
     FIFOF#(AxiStream512) xdmaAxiStreamInRxBuf <- mkFIFOF;
 
@@ -93,21 +93,27 @@ module mkTestUdpCmacRxTx(TestUdpCmacRxTx);
         let rawData <- randRawData.next;
         Bit#(PAYLOAD_EXT_WIDTH) extRawData = zeroExtend(rawData);
         Vector#(PAYLOAD_FRAME_NUM, Bit#(AXIS512_TDATA_WIDTH)) rawDataVec = unpack(extRawData);
+        // AxiStream512 axiStream = AxiStream {
+        //     tData: rawDataVecReg[inputFrameCount],
+        //     tKeep: setAllBits,
+        //     tLast: False,
+        //     tUser: 0
+        // };
         AxiStream512 axiStream = AxiStream {
-            tData: rawDataVecReg[inputFrameCount],
+            tData: setAllBits,
             tKeep: setAllBits,
             tLast: False,
             tUser: 0
         };
 
-        if (inputFrameCount == 0) begin
-            rawDataVecReg <= rawDataVec;
-            axiStream.tData = rawDataVec[0];
-        end
+        // if (inputFrameCount == 0) begin
+        //     rawDataVecReg <= rawDataVec;
+        //     axiStream.tData = rawDataVec[0];
+        // end
 
         if (nextFrameCount == fromInteger(payloadFrameNum)) begin
             axiStream.tLast = True;
-            axiStream.tKeep = axiStream.tKeep >> valueOf(EXTRA_BYTE_NUM);
+            //axiStream.tKeep = axiStream.tKeep >> valueOf(EXTRA_BYTE_NUM);
             inputFrameCount <= 0;
             inputCaseCount <= inputCaseCount + 1;
         end

fpga/common/bsv/XdmaUdpIpEthBypassCmacRxTx.bsv

@@ -36,7 +36,7 @@ typedef 32'hC0A80102 SOURCE_IP_ADDR;
 
 typedef 32'h00000000 TEST_NET_MASK;
 typedef 32'h00000000 TEST_GATE_WAY;
-typedef 88 TEST_UDP_PORT;
+typedef UDP_PORT_RDMA TEST_UDP_PORT;
 typedef 2048 TEST_PAYLOAD_SIZE;
 
 
@@ -97,8 +97,10 @@ module mkUdpIpEthBypassRxTxForXdma(UdpIpEthBypassRxTxForXdma);
     endrule
 
     rule recvUdpIpMetaData;
-        let udpIpMetaData = udpIpEthBypassRxTx.udpIpMetaDataRxOut.first;
         udpIpEthBypassRxTx.udpIpMetaDataRxOut.deq;
+    endrule
+
+    rule recvMacMetaData;
         udpIpEthBypassRxTx.macMetaDataRxOut.deq;
     endrule
 
@@ -121,6 +123,29 @@ module mkUdpIpEthBypassRxTxForXdma(UdpIpEthBypassRxTxForXdma);
     interface cmacAxiStreamTxOut = cmacAxiStream512TxOut;
 endmodule
 
+interface RawUdpIpEthBypassRxTxForXdma;
+    interface RawAxiStreamSlave#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH)  xdmaAxiStreamTxIn;
+    interface RawAxiStreamMaster#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH) xdmaAxiStreamRxOut;
+    interface RawAxiStreamSlave#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH)  cmacAxiStreamRxIn;
+    interface RawAxiStreamMaster#(AXIS512_TKEEP_WIDTH, AXIS_TUSER_WIDTH) cmacAxiStreamTxOut;
+endinterface
+
+(* synthesize *)
+module mkRawUdpIpEthBypassRxTxForXdma(RawUdpIpEthBypassRxTxForXdma);
+    let udpIpEthBypass <- mkUdpIpEthBypassRxTxForXdma;
+
+    let rawXdmaAxiStreamTxIn <- mkFifoInToRawAxiStreamSlave(udpIpEthBypass.xdmaAxiStreamTxIn);
+    let rawXdmaAxiStreamRxOut <- mkFifoOutToRawAxiStreamMaster(udpIpEthBypass.xdmaAxiStreamRxOut);
+    let rawCmacAxiStreamRxIn <- mkFifoInToRawAxiStreamSlave(udpIpEthBypass.cmacAxiStreamRxIn);
+    let rawCmacAxiStreamTxOut <- mkFifoOutToRawAxiStreamMaster(udpIpEthBypass.cmacAxiStreamTxOut);
+
+    interface xdmaAxiStreamTxIn = rawXdmaAxiStreamTxIn;
+    interface xdmaAxiStreamRxOut = rawXdmaAxiStreamRxOut;
+    interface cmacAxiStreamRxIn = rawCmacAxiStreamRxIn;
+    interface cmacAxiStreamTxOut = rawCmacAxiStreamTxOut;
+
+endmodule
+
 
 interface XdmaUdpIpEthBypassCmacRxTx;
     // Interface with CMAC IP