fix timing

datenlord · Mar 28, 2024 · 2eebbe2 · 2eebbe2
1 parent ac28cc7
commit 2eebbe2
Showing 1 changed file with 7 additions and 1 deletion.
diff --git a/src/includes/EthUtils.bsv b/src/includes/EthUtils.bsv
@@ -363,11 +363,17 @@ module mkSizedBramFifoToFifoOut#(
 )(FifoOut#(dType)) provisos(Bits#(dType, dSize), Add#(1, a__, dSize), FShow#(dType));
 
     FIFOF#(dType) fifo <- mkSizedBRAMFIFOF(depth);
+    // to fix timing, BRAM fifo is complex at it's output port.
+    FIFOF#(dType) outBuffer <- mkFIFOF;  
     rule doEnq;
         fifo.enq(pipe.first);
         pipe.deq;
     endrule
-    return convertFifoToFifoOut(fifo);
+    rule doDeq;
+        outBuffer.enq(fifo.first);
+        fifo.deq;
+    endrule
+    return convertFifoToFifoOut(outBuffer);
 endmodule
 
 module mkSizedFifoToFifoOut#(