Add initial support for Olimex iCE40HX8K-EVB

.gitignore

@@ -0,0 +1,9 @@
+tmp/*
+sim/darksocv
+sim/darksocv.vcd
+*.ld
+*.lst
+*.map
+*.mem
+*.s
+*.o

boards/olimex_ice40hx8k/README.md

@@ -0,0 +1,17 @@
+## AVNET Microboard LX9
+
+The old AVNET Microboard LX9 is my preferred development board because is
+small, easy to connect to the development environment and very complete,
+with integrated JTAG, USB/serial and Ethernet! 
+
+The board includes:
+
+- a XC6SLX9 FPGA w/ 324 pins
+- lots of clocks: 40MHz, 66MHz and 100MHz
+- on-board USB/serial (CP2102)
+- on-board JTAG
+- on-board SPI FLASH
+- on-board 10/100Mbps ethernet PHY
+- on-board DDR
+- four LEDs
+- some few GPIO pins

boards/olimex_ice40hx8k/darksocv.mk

@@ -0,0 +1,110 @@
+#
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# 
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+# 
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+# 
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+#
+# ===8<--------------------------------------------------------- cut here!
+#
+# The general concept is based in the article:
+# 
+# https://www.fpgarelated.com/showarticle/786.php
+#
+# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with
+# all commands executed and the respective options, it is possible change
+# some options in the ISE and check the file in order to understand how
+# enable/disable the different options.
+# 
+
+# board Avnet Microboard LX9
+#BOARD = avnet_microboard_lx9
+#DEVICE = xc6slx9-csg324-2
+
+# board Xilinx AC701 A200
+#BOARD = xilinx_ac701_a200
+#DEVICE = xc7a200t-fbg676-2
+
+# board QMTech SDRAM LX16
+#BOARD = qmtech_sdram_lx16
+#DEVICE = xc6slx16-ftg256-2
+
+# board Olimex iCE40HX8k-EVB
+BOARD = olimex_ice40hx8k
+PNR = nextpnr-ice40
+#PNR = arachne-pnr
+
+ISE = ../boards/$(BOARD)
+RTL = ../rtl
+SRC = ../src
+TMP = ../tmp
+
+BLIF = $(TMP)/darksocv.blif
+JSON = $(TMP)/darksocv.json
+PCF = $(ISE)/darksocv.pcf
+ASC = $(TMP)/darksocv.asc
+BIT = $(TMP)/darksocv.bit
+
+PRJS = $(ISE)/darksocv.prj
+RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh
+
+ifdef HARVARD
+ BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem
+else
+ BOOT = $(SRC)/darksocv.mem
+endif
+
+ifeq ($(PNR),nextpnr-ice40)
+PNR_NEXT = 1
+else
+PNR_NEXT = 0
+endif
+
+default: all
+
+$(BLIF): $(RTLS)
+ yosys -q -p "read_verilog -noautowire -DOLIMEX_ICE40HX8K=1 $(RTLS); synth_ice40 -top darksocv -blif $@"
+
+$(JSON): $(RTLS)
+ yosys -q -p "read_verilog -noautowire -DOLIMEX_ICE40HX8K=1 $(RTLS); synth_ice40 -top darksocv -json $@"
+
+$(ASC): $(if $(PNR_NEXT),$(JSON),$(BLIF))
+ifeq ($(PNR_NEXT),1)
+ $(PNR) --hx8k --package ct256 --pcf $(PCF) $(PNRFLAGS) --asc $@ --json $<
+else
+ $(PNR) -d 8k -P ct256 -p $(PCF) $(PNRFLAGS) -o $@ $<
+endif
+
+$(BIT): $(ASC)
+ icepack $< $@
+
+.PHONY: all
+all: $(BIT) $(BOOT) $(RTLS)
+
+install: $(BIT)
+ iceprog $<
+
+clean:
+ -rm -v $(TMP)/*

boards/olimex_ice40hx8k/darksocv.pcf

@@ -0,0 +1,16 @@
+set_io XCLK J3
+
+set_io XRES K11
+
+set_io LED[3] E4 # PIO3_00/IOL_1A 
+set_io LED[2] B2 # PIO3_01/IOL_1B
+set_io LED[1] R16
+set_io LED[0] M12
+
+set_io UART_RXD L11
+set_io UART_TXD T16
+
+set_io DEBUG[3] P15 # TDO
+set_io DEBUG[2] P14 # TCK
+set_io DEBUG[1] R15 # TMS
+set_io DEBUG[0] R14 # TDI

rtl/config.vh

@@ -75,7 +75,7 @@
 // performance impact. Note: threading is currently supported only in the
 // 3-stage pipeline version.
 
-`define __THREADING__
+//`define __THREADING__
 
 // performance measurement:
 //
@@ -96,7 +96,7 @@
 // designed for DSP applications. with some effort (low level machine
 // code), it is possible peak 100MMAC/s @100MHz.
 
-`define __MAC16X16__
+//`define __MAC16X16__
 
 // RV32I vs RV32E:
 //
@@ -116,11 +116,12 @@
 // the stack can be positioned in the top of RAM and does not match with the
 // .data.
 
-`define __HARVARD__
+`define __RESETPC__ 32'd0
+`define __RESETSP__ 32'd8192
 
 // full harvard architecture:
 // 
-// When defined, enforses that the instruction and data buses are connected
+// When defined, enforces that the instruction and data buses are connected
 // to fully separate memory banks. Although the darkriscv always use
 // harvard architecture in the core, with separate instruction and data
 // buses, the logic levels outside the core can use different architectures
@@ -134,8 +135,7 @@
 //
 // for spartan-7 devices, always use full harvard architecture!
 
-`define __RESETPC__ 32'd0
-`define __RESETSP__ 32'd8192
+`define __HARVARD__
 
 // board definition:
 // 
@@ -192,16 +192,65 @@
  `define BOARD_CK 50000000
 `endif
 
+`ifdef OLIMEX_ICE40HX8K
+ `define BOARD_ID 4
+ `define BOARD_CK_REF 100000000
+ `ifdef __3STAGE__
+ `ifdef __THREADING__
+ `define BOARD_CK_30
+ `elsif __MAC16X16__
+ `define BOARD_CK_25
+ `else
+ `define BOARD_CK_40
+ `endif
+ `else
+ `ifdef __MAC16X16__
+ `define BOARD_CK_16
+ `else
+ `define BOARD_CK_25
+ `endif
+ `endif
+ `ifdef BOARD_CK_40
+ `define BOARD_CK 40000000
+ `define BOARD_CK_DIVR 4'd4
+ `define BOARD_CK_DIVF 7'd31
+ `define BOARD_CK_DIVQ 3'd4
+ `define BOARD_CK_FILTER 3'd2
+ `elsif BOARD_CK_30
+ `define BOARD_CK 30000000
+ `define BOARD_CK_DIVR 4'd4
+ `define BOARD_CK_DIVF 7'd47
+ `define BOARD_CK_DIVQ 3'd5
+ `define BOARD_CK_FILTER 3'd2
+ `elsif BOARD_CK_25
+ `define BOARD_CK 25000000
+ `define BOARD_CK_DIVR 4'd0
+ `define BOARD_CK_DIVF 7'd7
+ `define BOARD_CK_DIVQ 3'd5
+ `define BOARD_CK_FILTER 3'd5
+ `elsif BOARD_CK_16
+ `define BOARD_CK 16250000
+ `define BOARD_CK_DIVR 4'd4
+ `define BOARD_CK_DIVF 7'd51
+ `define BOARD_CK_DIVQ 3'd6
+ `define BOARD_CK_FILTER 3'd2
+ `else
+ `undef WARNING_PREPROCESSOR_SHOULD_NOT_REACH_THIS_LOCATION
+ `endif
+`endif
+
 `ifndef BOARD_ID
  `define BOARD_ID 0 
  `define BOARD_CK 100000000 
 `endif
 
 `ifdef BOARD_CK_REF
+`ifndef BOARD_CK
  `define BOARD_CK (`BOARD_CK_REF * `BOARD_CK_MUL / `BOARD_CK_DIV)
 `endif
+`endif
 
-// darkuart baudrate automtically calculated according to board clock:
+// darkuart baudrate automatically calculated according to board clock:
 
 `ifndef __UARTSPEED__ 
  `define __UARTSPEED__ 115200

rtl/darksocv.v

@@ -122,6 +122,7 @@ module darksocv
  //`define BOARD_CK (`BOARD_CK_REF * `BOARD_CK_MUL / `BOARD_CK_DIV)
 
  wire DCM_LOCKED;
+ wire CLK;
 
  // useful script to calculate MUL/DIV values:
  // 
@@ -130,7 +131,8 @@ module darksocv
  // example: reference w/ 66MHz, m=19, d=13 and fx=97.4MHz. not so useful after I discovered 
  // that my evaluation board already has external clock generator :D
 
- DCM_SP #(
+`ifndef OLIMEX_ICE40HX8K
+ DCM_SP #(
  .CLKDV_DIVIDE(2.0), // CLKDV divide value
  // (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
  .CLKFX_DIVIDE(`BOARD_CK_DIV), // Divide value on CLKFX outputs - D - (1-32)
@@ -169,6 +171,22 @@ module darksocv
  //.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement input
  .RST(IRES[7]) // 1-bit input: Active high reset input
  );
+`else
+ SB_PLL40_CORE #(
+ .FEEDBACK_PATH("SIMPLE"),
+ .DIVR(`BOARD_CK_DIVR),
+ .DIVF(`BOARD_CK_DIVF),
+ .DIVQ(`BOARD_CK_DIVQ),
+ .FILTER_RANGE(`BOARD_CK_FILTER)
+ )
+ SB_PLL40_CORE_inst (
+ .LOCK(DCM_LOCKED),
+ .RESETB(IRES[7]),
+ .BYPASS(1'b0),
+ .REFERENCECLK(XCLK),
+ .PLLOUTCORE(CLK)
+ );
+`endif
 
  reg [7:0] DRES = -1;
 
@@ -672,4 +690,4 @@ module darksocv
 
  assign DEBUG = { GPIOFF[0], XTIMER, WR, RD }; // UDEBUG;
 
-endmodule
+endmodule

src/Makefile

@@ -61,9 +61,9 @@ endif
  OD = $(CCPATH)/$(CROSS)-objdump
  CPP = $(CCPATH)/$(CROSS)-cpp
 
-CCFLAGS = -Wall -I./include -Os -march=$(ARCH) -D__RISCV__ -DBUILD="\"$(BUILD)\"" -DARCH="\"$(ARCH)\""
+CCFLAGS = -Wall -I./include -Os -march=$(ARCH) -mabi=ilp32e -D__RISCV__ -DBUILD="\"$(BUILD)\"" -DARCH="\"$(ARCH)\""
 ASFLAGS = -march=$(ARCH)
-LDFLAGS = -T$(PROJ).ld -Map=$(PROJ).map # -Ttext=0
+LDFLAGS = -T$(PROJ).ld -Map=$(PROJ).map -m elf32lriscv # -Ttext=0
 CPFLAGS = -P 
 
 #CCFLAGS += -mcmodel=medany -mexplicit-relocs # relocable clode