The LC 3 ISA
This is the Appendix A part of the data backups of the original LC-3 appendices.
The Instruction Set Architecture (ISA) of LC-3 is defined as follows:
Memory Address Space - 16 bits, corresponding to 216 locations, each containing one word (16 bits). Addresses are numbered from 0 (i.e, x0000) to 65,535 (i.e., xFFFF). Addresses are used to identify memory locations and memory-mapped I/O device registers. Certain regions of memory are reserved for special uses, as described in Figure A.1 below.
Bit Numbering - Bits of all quantities are numbered, from right to left, starting with bit 0. The leftmost bit of the contents of a memory location is bit 15.
Instructions - Instructions are 16 bits wide. Bits [15:12] specify the opcode (operation to be performed), bits [11:0] provide further information that is needed to execute the instruction. The specific operation of each LC-3 instruction is described in Section A.3.
Figure A.1 A memory map of the LC-3
Illegal Opcode Exception - Bits [15:12] = 1101 has not been specified. If an instruction contains 1101 in bits [15:12], an illegal opcode exception occurs. Section A.4 explains what happens.
Program Counter (PC) - A 16-bit register containing the address of the next instruction to be processed.
General Purpose Registers - Eight 16-bit registers, numbered from 000 to 111.
Condition Codes - Three 1-bit registers: N (negative), Z (zero), and P(positive). Load instructions (LD, LDI, LDR, and LEA) and operate instructions (ADD, AND, and NOT) each load a result into one of the eight general purpose registers. The condition codes are set, based on whether that result, taken as a 16-bit 2’s complement integer, is negative (N = 1; Z, P = 0), zero (Z = 1;N, P = 0), or positive (P = 1;N, Z = 0). All other LC-3 instructions leave the condition codes unchanged.
Memory-Mapped I/O - Input and output are handled by load/store (LDI/STI, LDR/STR) instructions using memory addresses to designate each I/O device register. Addresses xFE00 through xFFFF have been allocated to represent the addresses of I/O devices. See Figure A.1. Also, Table A.3 lists each of the relevant device registers that have been identified for the LC-3 thus far, along with their corresponding assigned addresses from the memory address space.
Interrupt processing - I/O devices have the capability of interrupting the processor. Section A.4 describes the mechanism.
Priority Level - The LC-3 supports eight levels of priority. Priority level 7 (PL7) is the highest; PL0 is the lowest. The priority level of the currently executing process is specified in bits PSR[10:8].
Processor Status Register (PSR) - A 16-bit register, containing status information about the currently executing process. Seven bits of the PSR have been defined thus far. PSR[15] specifies the privilege mode of the executing process. PSR[10:8] specifies the priority level of the currently executing process. PSR[2:0] contains the condition codes. PSR[2] is N, PSR[1] is Z, and PSR[0] is P.
Privilege Mode - The LC-3 specifies two levels of privilege, Supervisor mode (privileged) and User mode (unprivileged). Interrupt service routines execute in Supervisor mode. The privilege mode is specified by PSR[15]. PSR[15] = 0 indicates Supervisor mode; PSR[15] = 1 indicates User mode.
Privilege Mode Exception - The RTI instruction executes in Supervisor mode. If the processor attempts to execute an RTI instruction while in User mode, a privilege mode exception occurs. Section A.4 explains what happens.
** Supervisor Stack -** A region of memory in supervisor space accessible via the Supervisor Stack Pointer (SSP). When PSR[15] = 0, the stack pointer (R6) is SSP.
User Stack - A region of memory in user space accessible via the User Stack Pointer (USP). When PSR[15] = 1, the stack pointer (R6) is USP.
The notation in Table A.1 will be helpful in understanding the descriptions of the LC-3 instructions (Section A.3).
The LC-3 supports a rich, but lean, instruction set. Each 16-bit instruction consists of an opcode (bits[15:12]) plus 12 additional bits to specify the other information that is needed to carry out the work of that instruction. Figure A.2 summarizes the 15 different opcodes in the LC-3 and the specification of the remaining bits of each instruction. The 16th 4-bit opcode is not specified, but is reserved for future use. In the following pages, the instructions will be described in greater detail. For each instruction, we show the assembly language representation, the format of the 16-bit instruction, the operation of the instruction, an English-language description of its operation, and one or more examples of the instruction. Where relevant, additional notes about the instruction are also provided.
Table A.1 - Notational Conventions
| Notation | Meaning |
|---|---|
| xNumber | The number in hexadecimal notation. |
| #Number | The number in decimal notation. |
| A[l:r] | The field delimited by bit [l] on the left and bit [r] on the right, of the datum A. For example, if PC contains 0011001100111111, then PC[15:9] is 0011001. PC[2:2] is 1. If l and r are the same bit number, the notation is usually abbreviated PC[2]. |
| BaseR | Base Register; one of R0..R7, used in conjunction with a six-bit offset to compute Base+offset addresses. |
| DR | Destination Register; one of R0..R7, which specifies which register the result of an instruction should be written to. |
| imm5 | A 5-bit immediate value; bits [4:0] of an instruction when used as a literal (immediate) value. Taken as a 5-bit, 2’s complement integer, it is sign-extended to 16 bits before it is used. Range: −16..15. |
| LABEL | An assembly language construct that identifies a location symbolically (i.e., by means of a name, rather than its 16-bit address). |
| mem[address] | Denotes the contents of memory at the given address. |
| offset6 | A 6-bit value; bits [5:0] of an instruction; used with the Base+offset addressing mode. Bits [5:0] are taken as a 6-bit signed 2’s complement integer, sign-extended to 16 bits and then added to the Base Register to form an address. Range: −32..31. |
| PC | Program Counter; 16-bit register that contains the memory address of the next instruction to be fetched. For example, during execution of the instruction at address A, the PC contains address A + 1, indicating the next instruction is contained in A + 1. |
| PCoffset9 | A 9-bit value; bits [8:0] of an instruction; used with the PC+offset addressing mode. Bits [8:0] are taken as a 9-bit signed 2’s complement integer, sign-extended to 16 bits and then added to the incremented PC to form an address. Range −256..255. |
| PCoffset11 | An 11-bit value; bits [10:0] of an instruction; used with the JSR opcode to compute the target address of a subroutine call. Bits [10:0] are taken as an 11-bit 2’s complement integer, sign-extended to 16 bits and then added to the incremented PC to form the target address. Range −1024..1023. |
| PSR | Processor Status Register; 16-bit register that contains status information of the process that is running. SR[15] = privilege mode. PSR[2:0] contains the condition codes. PSR[2] = N, PSR[1] = Z, PSR[0] = P. |
| setcc() | Indicates that condition codes N, Z, and P are set based on the value of the result written to DR. If the value is negative, N = 1, Z = 0, P = 0. If the value is zero, N = 0, Z = 1, P = 0. If the value is positive, N = 0, Z = 0, P = 1. |
| SEXT(A) | Sign-extend A. The most significant bit of A is replicated as many times as necessary to extend A to 16 bits. For example, if A = 110000, then SEXT(A) = 1111 1111 1111 0000. |
| SP | The current stack pointer. R6 is the current stack pointer. There are two stacks, one for each privilege mode. SP is SSP if PSR[15] = 0; SP is USP if PSR[15] = 1. SR, SR1, SR2 Source Register; one of R0..R7 which specifies the register from which a source operand is obtained. |
| SSP | The Supervisor Stack Pointer. |
| trapvect8 | An 8-bit value; bits [7:0] of an instruction; used with the TRAP opcode to determine the starting address of a trap service routine. Bits [7:0] are taken as an unsigned integer and zero-extended to 16 bits. This is the address of the memory location containing the starting address of the corresponding service routine. Range 0..255. |
| USP | The User Stack Pointer. |
| ZEXT(A) | Zero-extend A. Zeros are appended to the leftmost bit of A to extend it to 16 bits. For example, if A = 110000, then ZEXT(A) = 0000 0000 0011 0000. |
Figure A.2 Format of the entire LC-3 instruction set. Note: + indicates instructions that modify condition codes
| Trap Vector | Assembler Name | Description |
|---|---|---|
| x20 | GETC | Read a single character from the keyboard. The character is not echoed onto the console. Its ASCII code is copied into R0. The high eight bits of R0 are cleared. |
| x21 | OUT | Write a character in R0[7:0] to the console display. |
| x22 | PUTS | Write a string of ASCII characters to the console display. The characters are contained in consecutive memory locations, one character per memory location, starting with the address specified in R0. Writing terminates with the occurrence of x0000 in a memory location. |
| x23 | IN | Print a prompt on the screen and read a single character from the keyboard. The character is echoed onto the console monitor, and its ASCII code is copied into R0. The high eight bits of R0 are cleared. |
| x24 | PUTSP | Write a string of ASCII characters to the console. The characters are contained in consecutive memory locations, two characters per memory location, starting with the address specified in R0. The ASCII code contained in bits [7:0] of a memory location is written to the console first. Then the ASCII code contained in bits [15:8] of that memory location is written to the console. (A character string consisting of an odd number of characters to be written will have x00 in bits [15:8] of the memory location containing the last character to be written.) Writing terminates with the occurrence of x0000 in a memory location. |
| x25 | HALT | Halt execution and print a message on the console. |
| Address I/O | Register Name I/O | Register Function |
|---|---|---|
| xFE00 | Keyboard status register | Also known as KBSR. The ready bit (bit [15]) indicates if |
| the keyboard has received a new character. | ||
| xFE02 | Keyboard data register | Also known as KBDR. Bits [7:0] contain the last |
| character typed on the keyboard. | ||
| xFE04 | Display status register | Also known as DSR. The ready bit (bit [15]) indicates if |
| the display device is ready to receive another character to print on the screen. | ||
| xFE06 | Display data register | Also known as DDR. A character written in the low byte |
| of this register will be displayed on the screen. | ||
| xFFFE | Machine control register | Also known as MCR. Bit [15] is the clock enable bit. When cleared, instruction processing stops. |
Events external to the program that is running can interrupt the processor. A common example of an external event is interrupt-driven I/O. It is also the case that the processor can be interrupted by exceptional events that occur while the program is running that are caused by the program itself. An example of such an "internal” event is the presence of an unused opcode in the computer program that is running.
Associated with each event that can interrupt the processor is an 8-bit vector that provides an entry point into a 256-entry interrupt vector table. The starting address of the interrupt vector table is x0100. That is, the interrupt vector table “app-a” — 2004/5/21 — page 544 — #24 544 appendix a The LC-3 ISA occupies memory locations x0100 to x01FF. Each entry in the interrupt vector table contains the starting address of the service routine that handles the needs of the corresponding event. These service routines execute in Supervisor mode.
Half (128) of these entries, locations x0100 to x017F, provide the starting addresses of routines that service events caused by the running program itself. These routines are called exception service routines because they handle exceptional events, that is, events that prevent the program from executing normally. The other half of the entries, locations x0180 to x01FF, provide the starting addresses of routines that service events that are external to the program that is running, such as requests from I/O devices. These routines are called interrupt service routines.
At this time, an LC-3 computer system provides only one I/O device that can interrupt the processor. That device is the keyboard. It interrupts at priority level PL4 and supplies the interrupt vector x80.
An I/O device can interrupt the processor if it wants service, if its Interrupt Enable (IE) bit is set, and if the priority of its request is greater than the priority of the program that is running.
Assume a program is running at a priority level less than 4, and someone strikes a key on the keyboard. If the IE bit of the KBSR is 1, the currently executing program is interrupted at the end of the current instruction cycle. The interrupt service routine is initiated as follows:
- The processor sets the privilege mode to Supervisor mode (PSR[15] = 0).
- The processor sets the priority level to PL4, the priority level of the interrupting device (PSR[10:8] = 100).
- R6 is loaded with the Supervisor Stack Pointer (SSP) if it does not already contain the SSP.
- The PSR and PC of the interrupted process are pushed onto the Supervisor Stack.
- The keyboard supplies its 8-bit interrupt vector, in this case x80.
- The processor expands that vector to x0180, the corresponding 16-bit address in the interrupt vector table.
- The PC is loaded with the contents of memory location x0180, the address of the first instruction in the keyboard interrupt service routine.
The processor then begins execution of the interrupt service routine.
The last instruction executed in an interrupt service routine is RTI. The top two elements of the Supervisor Stack are popped and loaded into the PC and PSR registers. R6 is loaded with the appropriate stack pointer, depending on the new value of PSR[15]. Processing then continues where the interrupted program left off.
At this time, the LC-3 ISA specifies two exception conditions: privilege mode violation and illegal opcode. The privilege mode violation occurs if the processor encounters the RTI instruction while running in User mode. The illegal opcode exception occurs if the processor encounters the unused opcode (Bits [15:12] = 1101) in the instruction it is is processing.
Exceptions are handled as soon as they are detected. They are initiated very much like interrupts are initiated, that is:
- The processor sets the privilege mode to Supervisor mode (PSR[15] = 0).
- R6 is loaded with the Supervisor Stack Pointer (SSP) if it does not already contain the SSP.
- The PSR and PC of the interrupted process are pushed onto the Supervisor Stack.
- The exception supplies its 8-bit vector. In the case of the Privilege mode violation, that vector is x00. In the case of the illegal opcode, that vector is x01.
- The processor expands that vector to x0100 or x0101, the corresponding 16-bit address in the interrupt vector table.
- The PC is loaded with the contents of memory location x0100 or x0101, the address of the first instruction in the corresponding exception service routine.
The processor then begins execution of the exception service routine.
The details of the exception service routine depend on the exception and the way in which the operating system wishes to handle that exception.
In many cases, the exception service routine can correct any problem caused by the exceptional event and then continue processing the original program. In those cases the last instruction in the exception service routine is RTI, which pops the top two elements from the Supervisor Stack and loads them into the PC and PSR registers. The program then resumes execution with the problem corrected.
In some cases, the cause of the exceptional event is so catastrophic that the exception service routine removes the program from further processing.
Another difference between the handling of interrupts and the handling of exceptions is the priority level of the processor during the execution of the service routine. In the case of exceptions, we normally do not change the priority level when we service the exception. The priority level of a program is the urgency with which it needs to be executed. In the case of the two exceptions specified by the LC-3 ISA, the urgency of a program is not changed by the fact that a privilege mode violation occurred or there was an illegal opcode in the program.