This is the course project of ECE6913 Computer System Architechture, intructed by Professor Brandon Reagon.
- LAB1 - implement a five stage architechture
- LAB2 - Implement a five stage pipeline with branche prediction and avoid harzard forwarding
- LAB3 - Implement a branch predictor with 2-bit saturating counters for m bit LSB of the instruction
- LAB4 - Imulated a 2 level non-inclusive cache, capable of loading data when read miss and evict data with round-robin when cache is full