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Add dff-name-style #1983

Merged
merged 6 commits into from
Oct 7, 2024
Merged

Add dff-name-style #1983

merged 6 commits into from
Oct 7, 2024

Commits on Oct 6, 2024

  1. verilog: CST: format expresion_test.cc

    @IEncinas10
    IEncinas10 committed Oct 6, 2024
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  2. verilog: tools: lint: add integration test for forbid_negative_array_dim

    @IEncinas10
    IEncinas10 committed Oct 6, 2024
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  3. CST: add helpers for nonblocking assignments 

    Add helpers to extract nonblocking assignments from a syntax tree.

Add helpers to extract left and right hand sides from nonblocking
assignments.
    @IEncinas10
    IEncinas10 committed Oct 6, 2024
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  4. CST: expression: add getters for IncrementDecrementExpression

    @IEncinas10
    IEncinas10 committed Oct 6, 2024
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  5. verilog: CST: statement: add header and expression getters for ifClause

    @IEncinas10
    IEncinas10 committed Oct 6, 2024
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  6. verilog: analysis: checkers: Add dff-name-style rule 

    dff-name-style-rule adds support for enforcing naming conventions for
registers.

It takes two parameters in the form of a comma separated list of
suffixes that are allowed for the input and output ports. If a list is
empty, it means that no checks will be performed in the respective
field.

In addition to checking suffixes, the rule also enforces that the base
(or prefix) is shared between the input and output of the register.

Furthermore, it also allows for numbered identifiers, where the number
means the pipeline stage where the signal originates from.

There are other two parameters meant to restrict the rule in some
common corner-cases:

  1. Common reset/flush blocks where default values might be assigned
     can be waived using their `if` condition

  2. Variables on which we don't want the rule to act can be waived
     using a regular expression.
    @IEncinas10
    IEncinas10 committed Oct 6, 2024
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