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Wrong formatting of constraints blocks #445

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msfschaffner opened this issue Sep 11, 2020 · 19 comments · Fixed by #706
Closed

Wrong formatting of constraints blocks #445

msfschaffner opened this issue Sep 11, 2020 · 19 comments · Fixed by #706
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formatter Verilog code formatter issues good first issue Good for newcomers

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@msfschaffner
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Verible erroneously reformats the following blocks into one-liners.

before:

constraint c_iv {
    if (fixed_iv_en) {
      aes_iv == fixed_iv
    };
  }

  constraint c_operation {
     if (fixed_operation_en) {
         aes_operation == fixed_operation
     };
  }

after:

constraint c_iv {if (fixed_iv_en) {aes_iv == fixed_iv};}

constraint c_operation {if (fixed_operation_en) {aes_operation == fixed_operation};}
@msfschaffner
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b/168312418

@fangism fangism added the formatter Verilog code formatter issues label Sep 11, 2020
@fangism fangism added the good first issue Good for newcomers label Sep 11, 2020
@vasantteja
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Can I assign this to myself?

@fangism
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fangism commented Sep 15, 2020

Yes, thank you for volunteering!

Tips: examine verible-verilog-syntax --printtree to see the internal syntax tree structure.
verible-verilog-format --show_token_partition_tree (optionally --show_inter_token_info) will show you the formatter internal representation as a hierarchical tree of token ranges.

Feel free to ask any questions to help get you going.

@fangism
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fangism commented Sep 22, 2020

@vasantteja Checking in, need any help or have any questions?

fangism referenced this issue in hzeller/opentitan Sep 22, 2020
$ verible-verilog-format --version
v0.0-620-gb46d580
Commit  2020-09-22
Built   2020-09-22T16:35:05Z

Invocation:

$ verible-verilog-format --formal_parameters_indentation=indent --named_parameter_indentation=indent --named_port_indentation=indent --port_declarations_indentation=indent --inplace ${filename}
@fangism
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fangism commented Sep 28, 2020

@vasantteja Checking in, need any help or have any questions?

@vasantteja
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@fangism sorry, I was traveling and I couldn't take a look at this. I will reach out to you if I have any doubts. Thanks for the patience.

@vasantteja vasantteja removed their assignment Feb 17, 2021
@ghost ghost self-assigned this Mar 19, 2021
@ghost
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ghost commented Mar 23, 2021

Hi @msfschaffner,
Just for clarification: all constraints blocks should be expanded?

For example I've found in an Ibex source code such line:

constraint only_vec_instr_c {soft only_vec_instr == 0;}

here: https://github.com/lowRISC/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_vector_cfg.sv#L32

and I'm not sure how to procceed.

Current PR expands all blocks except some simple one like that above:
https://github.com/google/verible/pull/706/files#diff-631e76d6700a6682c3bdc7f0aad5aa02a4f117aa2e8ae3e6b96c2ddaf34c92f1R9164

@msfschaffner
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Hey @ldalek-antmicro,

How about we standardize on something that only expands if the expression inside the outermost {} brackets contains more {} blocks or does not fit onto one single line?

@ghost
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ghost commented Mar 24, 2021

Thanks for an answer @msfschaffner

Got one more question about multi item constraints like:

constraint xx {
  aa == bb;
  cc == dd;
}

should them be fitted in one line (like you wrote above) or expanded (IMHO looks better expanded)?

@msfschaffner
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Yes, this also looks better to me in expanded form.

How about we only compact onto one line if the conditions mentioned above hold, AND the brackets only contain one expression?

@ghost
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ghost commented Mar 24, 2021

Okay, to sum up:

  1. If the expression contains brackets, expand, .e.g.
constraint xx {
  if (a) {
    b;
  }
}
  1. If the expression contains more than two expressions, expand, e.g.
constraint yy {
  a == b;
  c == d;
}
  1. If the expression doesn't fit, expand, e.g.
constraint yyyyyyyyyyyyyyyyyyyyy {
  aaaaaaaaaaaaaaaaaaaaaaa == bbbbbbbbbbbbbbbbbbbbbbbbb;
}
  1. otherwise, compact, e.g.
constraint only_vec_instr_c {soft only_vec_instr == 0;}

@msfschaffner
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Yes this SGTM!

hzeller added a commit that referenced this issue Mar 29, 2021
Expands constraints blocks with more than one partition, e.g. if-statements
```
constraint xx {
  if (a) b;
}
```

But keeps constraints blocks with simple statements unexpanded, e.g.

```
constraint only_vec_instr_c {soft only_vec_instr == 0;}
```

Fixes #445
@sriyerg
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sriyerg commented Apr 15, 2021

Okay, to sum up:

  1. If the expression contains brackets, expand, .e.g.
constraint xx {
  if (a) {
    b;
  }
}
  1. If the expression contains more than two expressions, expand, e.g.
constraint yy {
  a == b;
  c == d;
}
  1. If the expression doesn't fit, expand, e.g.
constraint yyyyyyyyyyyyyyyyyyyyy {
  aaaaaaaaaaaaaaaaaaaaaaa == bbbbbbbbbbbbbbbbbbbbbbbbb;
}
  1. otherwise, compact, e.g.
constraint only_vec_instr_c {soft only_vec_instr == 0;}

How will this get formatted?

  constraint foo_c {
    foo inside {[0:1]};
  }

Looks like the formatter will ignore this?

@hzeller
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hzeller commented Apr 15, 2021

That would fit in one line so would be formatted compactly:

$ verible-verilog-format - <<EOF
constraint foo_c {
    foo inside {[0:1]};
  }
EOF
constraint foo_c {foo inside {[0 : 1]};}

@ghost
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ghost commented Apr 15, 2021

But should be expanded (because of brackets).
This PR #761 fixes this. @hzeller can you look at it?

@sriyerg
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sriyerg commented Apr 15, 2021

But should be expanded (because of brackets).
This PR #761 fixes this. @hzeller can you look at it?

That's what I thought. Its a bit inconsistent then. This should be compacted too because it is not a conditional.

@ghost
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ghost commented Apr 15, 2021

@sriyerg Expression inside constraint block doesn't have to be a conditional to force expansion of such block.
@msfschaffner or does it?

@msfschaffner
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Hm... I believe the question is how rule 1. should be interpreted.

Should the expansion trigger on the conditional, or on the {} brackets.

It looks like conditionals with {} brackets are typically written a bit differently than inside {} statements, right @sriyerg?

If that is the case, shall we change that rule to only expand on conditional {} blocks?

@sriyerg
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sriyerg commented May 12, 2021

My preference TBH is to always expand constraints - i.e. put the expressions on a separate lines. It is the most consistent solution.

  constraint foo_c {
    expr1;
    expr2;
    ...
  }

If the exprs are either conditionals (if (x) { ...), loops (foreach (x[i]) {), constraint distributions ( x dist {), they must be expanded further.

nikhiljha pushed a commit to nikhiljha/verible that referenced this issue Sep 27, 2022
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