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Always expand coverpoint statements #813

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sriyerg opened this issue May 12, 2021 · 3 comments · Fixed by #851
Closed

Always expand coverpoint statements #813

sriyerg opened this issue May 12, 2021 · 3 comments · Fixed by #851
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formatter Verilog code formatter issues

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@sriyerg
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sriyerg commented May 12, 2021

Test case

  // Input to the formatter, preferably a reduced test case.
  cp_handshake_complete: coverpoint status {
    bins complete = {AlertAckComplete};
  }

Include any options or configuration used.

Actual output

  // This doesn't look right.
  cp_handshake_complete: coverpoint status {bins complete = {AlertAckComplete};}

Include any possible diagnostic messages from the formatter.

Expected or suggested output
Original is better.

Citations to published style guides would help.
Don't have one yet (I think), but will add soon.

@snsokolov
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Citations to published style guides would help.

Not sure about other style guides, this not regulated by the internal style guide.

It looks to me that formatter is trying to keep short statements like this on one line to make it more concise, but +1 that the original is looking more readable.

@msfschaffner
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If we decide to always expand coverpoints, it probably makes sense to do the same for constraints as well for consistency (as indicated by @sriyerg here: #445).

@fangism
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fangism commented Jun 9, 2021

General drive-by comment:
When there is a request to expand a section, the first thing I ask is whether a well-placed //comment can force that expansion, without having to add a control switch -- clang-format respects comments to force expansion in many places. Some of the formatter logic is intended to respect comments to do that. I understand that some users don't want to add extra comments.

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Labels
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5 participants