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verilog: CST: statement: add header and expression getters for ifClause
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IEncinas10 committed Sep 28, 2024
1 parent 1bf1d64 commit 9d2b098
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Showing 4 changed files with 101 additions and 0 deletions.
1 change: 1 addition & 0 deletions verilog/CST/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -749,6 +749,7 @@ cc_test(
deps = [
":match-test-utils",
":statement",
":verilog-matchers",
":verilog-nonterminals",
"//common/analysis:syntax-tree-search",
"//common/analysis:syntax-tree-search-test-utils",
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15 changes: 15 additions & 0 deletions verilog/CST/statement.cc
Original file line number Diff line number Diff line change
Expand Up @@ -520,4 +520,19 @@ const verible::SyntaxTreeNode *GetNonBlockingAssignmentRhs(
non_blocking_assignment, NodeEnum::kNonblockingAssignmentStatement, 3);
}

const verible::SyntaxTreeNode *GetIfClauseHeader(
const verible::SyntaxTreeNode &if_clause) {
return verible::GetSubtreeAsNode(if_clause, NodeEnum::kIfClause, 0);
}

const verible::SyntaxTreeNode *GetIfHeaderExpression(
const verible::SyntaxTreeNode &if_header) {
const verible::SyntaxTreeNode *paren_group =
verible::GetSubtreeAsNode(if_header, NodeEnum::kIfHeader, 2);

if (!paren_group) return nullptr;

return verible::GetSubtreeAsNode(*paren_group, NodeEnum::kParenGroup, 1);
}

} // namespace verilog
6 changes: 6 additions & 0 deletions verilog/CST/statement.h
Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,12 @@ const verible::SyntaxTreeNode *GetNonBlockingAssignmentLhs(
const verible::SyntaxTreeNode *GetNonBlockingAssignmentRhs(
const verible::SyntaxTreeNode &non_blocking_assignment);

const verible::SyntaxTreeNode *GetIfClauseHeader(
const verible::SyntaxTreeNode &if_clause);

const verible::SyntaxTreeNode *GetIfHeaderExpression(
const verible::SyntaxTreeNode &if_header);

} // namespace verilog

#endif // VERIBLE_VERILOG_CST_STATEMENT_H_
79 changes: 79 additions & 0 deletions verilog/CST/statement_test.cc
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@
#include "common/util/logging.h"
#include "gtest/gtest.h"
#include "verilog/CST/match_test_utils.h"
#include "verilog/CST/verilog_matchers.h"
#include "verilog/CST/verilog_nonterminals.h"
#include "verilog/analysis/verilog_analyzer.h"

Expand Down Expand Up @@ -1506,5 +1507,83 @@ TEST(GetNonBlockingAssignmentLhsTest, Various) {
}
}

TEST(GetIfClauseHeaderTest, Various) {
constexpr int kTag = 1; // value doesn't matter
const SyntaxTreeSearchTestCase kTestCases[] = {
{"module m;\n"
"always @(*)\n",
{kTag, "if (y)"},
" x = 1;\n"
"endmodule"},
{"module m;\n"
"always @(*) x = 1;\n"
"endmodule"},
};
for (const auto &test : kTestCases) {
TestVerilogSyntaxRangeMatches(
__FUNCTION__, test, [](const TextStructureView &text_structure) {
const auto &root = text_structure.SyntaxTree();
const auto &if_clauses =
verible::SearchSyntaxTree(*root, NodekIfClause());

std::vector<TreeSearchMatch> if_headers;
if_headers.reserve(if_clauses.size());
for (const auto &if_clause : if_clauses) {
const auto *header =
GetIfClauseHeader(verible::SymbolCastToNode(*if_clause.match));
if_headers.emplace_back(
TreeSearchMatch{header, {/* ignored context */}});
}
return if_headers;
});
}
}

TEST(GetIfClauseExpressionTest, Various) {
constexpr int kTag = 1; // value doesn't matter
const SyntaxTreeSearchTestCase kTestCases[] = {
{"module m;\n"
"always @(*) if(",
{kTag, "y"},
")\n "
"x = 1;\n"
"endmodule"},
{"module m;\n"
"always @(*) if(",
{kTag, "func()"},
") x = 1;\n"
"endmodule"},
{"module m;\n"
"always @(*) if(",
{kTag, "y"},
") begin\n",
"if(",
{kTag, "z"},
") x = 1;\n"
"end endmodule"},
{"module m;\n"
"always @(*) x = 1;\n"
"endmodule"},
};
for (const auto &test : kTestCases) {
TestVerilogSyntaxRangeMatches(
__FUNCTION__, test, [](const TextStructureView &text_structure) {
const auto &root = text_structure.SyntaxTree();
const auto &if_headers =
verible::SearchSyntaxTree(*root, NodekIfHeader());

std::vector<TreeSearchMatch> if_expressions;
if_expressions.reserve(if_headers.size());
for (const auto &if_header : if_headers) {
const auto *expression = GetIfHeaderExpression(
verible::SymbolCastToNode(*if_header.match));
if_expressions.emplace_back(
TreeSearchMatch{expression, {/* ignored context */}});
}
return if_expressions;
});
}
}

} // namespace
} // namespace verilog

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