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verilog: tools: ls: verilog-language-server: test: Marked places wher…
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…e hover is applied

Signed-off-by: Grzegorz Latosinski <[email protected]>
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glatosinski committed May 18, 2023
1 parent 13f94b0 commit 3f53a4b
Showing 1 changed file with 9 additions and 6 deletions.
15 changes: 9 additions & 6 deletions verilog/tools/ls/verilog-language-server_test.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1430,6 +1430,9 @@ TEST_F(VerilogLanguageServerSymbolTableTest, CheckReferenceUnknownSymbol) {
ASSERT_EQ(response_b["result"].size(), 0);
}

// Checks if the hover appears on port symbols
// In this test the hover for "sum" symbol in assign
// is checked
TEST_F(VerilogLanguageServerSymbolTableTest, HoverOverSymbol) {
absl::string_view filelist_content = "mod.v\n";
static constexpr absl::string_view //
Expand All @@ -1440,7 +1443,7 @@ TEST_F(VerilogLanguageServerSymbolTableTest, HoverOverSymbol) {
input reg [31:0] b,
output reg [31:0] sum);
always @(posedge clk) begin : addition
assign sum = a + b;
assign sum = a + b; // hover over sum
end
endmodule
)");
Expand All @@ -1456,8 +1459,8 @@ endmodule

GetResponse();

std::string hover_request =
HoverRequest("file://" + module.filename(), 2, 6, 12);
std::string hover_request = HoverRequest("file://" + module.filename(), 2,
/* line */ 6, /* column */ 12);

ASSERT_OK(SendRequest(hover_request));
json response = json::parse(GetResponse());
Expand All @@ -1483,7 +1486,7 @@ TEST_F(VerilogLanguageServerSymbolTableTest, HoverOverEnd) {
output reg [31:0] sum);
always @(posedge clk) begin : addition
assign sum = a + b;
end
end // hover over end
endmodule
)");

Expand All @@ -1498,8 +1501,8 @@ endmodule

GetResponse();

std::string hover_request =
HoverRequest("file://" + module.filename(), 2, 7, 3);
std::string hover_request = HoverRequest("file://" + module.filename(), 2,
/* line */ 7, /* column */ 3);

ASSERT_OK(SendRequest(hover_request));
json response = json::parse(GetResponse());
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