Build(deps): Bump third_party/sby from 117fb26 to daed0e1
#6006
Triggered via pull request
November 4, 2024 10:07
dependabot[bot]
Status
Success
Total duration
1h 13m 18s
Artifacts
49
main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 21s
Emit Workflow Info
0s
Style check
1m 25s
Verify README Correctness (Installation From Sources)
42m 20s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 33s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 7s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
25m 52s
Large Designs Tests
/
Opentitan (synthesis)
52m 24s
Large Designs Tests
/
VeeR-EH1 (synthesis)
4m 59s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
15m 28s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
32m 11s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
31m 0s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 18s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 33s
Parsing Tests
/
Summary Generation
1m 43s
Verify README Correctness (Download And Run Release)
0s
Annotations
4 warnings
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
binaries-asan
|
292 MB |
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binaries-package
|
23.1 MB |
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binaries-plugin
|
41.7 MB |
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binaries-pysynlig
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652 MB |
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binaries-release
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41.9 MB |
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bp_e_bp_unicore_cfg.edif
|
3.9 MB |
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bsg-logs
|
5.56 MB |
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bsg-outputs
|
1.72 MB |
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formal-verification-logs-simple
|
18.2 MB |
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formal-verification-logs-sv2v
|
62.8 MB |
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formal-verification-logs-yosys
|
50.5 MB |
|
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lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
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opentitan-logs-full
|
5.1 MB |
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opentitan-logs-quick
|
1.52 MB |
|
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plots_binaries-asan
|
107 KB |
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plots_binaries-package
|
98.5 KB |
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plots_binaries-plugin
|
91.7 KB |
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plots_binaries-pysynlig
|
142 KB |
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plots_binaries-release
|
109 KB |
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plots_blackparrot_synth_asic
|
199 KB |
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plots_blackparrot_synth_xilinx
|
102 KB |
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plots_blackparrot_synth_xilinx_python
|
181 KB |
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plots_build_tools
|
77.5 KB |
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plots_formal_verification_simple
|
117 KB |
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plots_formal_verification_sv2v
|
101 KB |
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plots_formal_verification_yosys
|
88 KB |
|
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plots_ibex_synth
|
46.7 KB |
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plots_ibex_synth_f4pga
|
79.8 KB |
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plots_opentitan_9d82960888_synth
|
151 KB |
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plots_opentitan_parse_report_full
|
85.4 KB |
|
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plots_opentitan_parse_report_quick
|
49.8 KB |
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plots_opentitan_synth
|
278 KB |
|
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plots_tests_asan_read_systemverilog
|
222 KB |
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plots_tests_asan_read_uhdm
|
168 KB |
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plots_tests_plugin_read_systemverilog
|
37.3 KB |
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plots_tests_plugin_read_uhdm
|
33.4 KB |
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plots_tests_release_read_systemverilog
|
35 KB |
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plots_tests_release_read_uhdm
|
32.3 KB |
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plots_veer_synth
|
36.1 KB |
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python_bp_e_bp_unicore_cfg.edif
|
3.9 MB |
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results_parsing_tests_asan_read_systemverilog
Expired
|
1.64 MB |
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results_parsing_tests_asan_read_uhdm
Expired
|
1.84 MB |
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results_parsing_tests_plugin_read_systemverilog
Expired
|
1.51 MB |
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results_parsing_tests_plugin_read_uhdm
Expired
|
1.76 MB |
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results_parsing_tests_release_read_systemverilog
Expired
|
1.5 MB |
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results_parsing_tests_release_read_uhdm
Expired
|
1.75 MB |
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tools
|
39.1 MB |
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top_artya7.bit
|
120 KB |
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