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chipsalliance / synlig Public

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Adjust Synlig Makefile to submodule changes #6003

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Adjust Synlig Makefile to submodule changes

Adjust Synlig Makefile to submodule changes #6003

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- Usage
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Usage Workflow file

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1 warning

Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

succeeded Oct 31, 2024 in 7m 0s

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