Fix debug logs for parsing tests #6000
Triggered via pull request
October 31, 2024 10:37
Status
Success
Total duration
1h 29m 13s
Artifacts
49
main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 31s
Emit Workflow Info
0s
Style check
1m 45s
Verify README Correctness (Installation From Sources)
42m 25s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 21s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 12s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
31m 9s
Large Designs Tests
/
Opentitan (synthesis)
1h 18m
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 50s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
17m 25s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
47m 21s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
40m 41s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 17s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 44s
Parsing Tests
/
Summary Generation
1m 43s
Verify README Correctness (Download And Run Release)
0s
Annotations
4 warnings
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
|
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
|
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
|
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
|
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
binaries-asan
|
288 MB |
|
binaries-package
|
22.6 MB |
|
binaries-plugin
|
40.9 MB |
|
binaries-pysynlig
|
646 MB |
|
binaries-release
|
41.4 MB |
|
bp_e_bp_unicore_cfg.edif
|
3.9 MB |
|
bsg-logs
|
5.56 MB |
|
bsg-outputs
|
1.72 MB |
|
formal-verification-logs-simple
|
18.8 MB |
|
formal-verification-logs-sv2v
|
62.9 MB |
|
formal-verification-logs-yosys
|
45.1 MB |
|
lowrisc_ibex_top_artya7_surelog_0.1.bit
|
107 KB |
|
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
628 KB |
|
opentitan-logs-full
|
5.08 MB |
|
opentitan-logs-quick
|
1.52 MB |
|
plots_binaries-asan
|
59.7 KB |
|
plots_binaries-package
|
32.7 KB |
|
plots_binaries-plugin
|
31 KB |
|
plots_binaries-pysynlig
|
70.2 KB |
|
plots_binaries-release
|
32.8 KB |
|
plots_blackparrot_synth_asic
|
266 KB |
|
plots_blackparrot_synth_xilinx
|
113 KB |
|
plots_blackparrot_synth_xilinx_python
|
235 KB |
|
plots_build_tools
|
78.8 KB |
|
plots_formal_verification_simple
|
118 KB |
|
plots_formal_verification_sv2v
|
114 KB |
|
plots_formal_verification_yosys
|
97.9 KB |
|
plots_ibex_synth
|
45.7 KB |
|
plots_ibex_synth_f4pga
|
80.5 KB |
|
plots_opentitan_9d82960888_synth
|
176 KB |
|
plots_opentitan_parse_report_full
|
104 KB |
|
plots_opentitan_parse_report_quick
|
48.8 KB |
|
plots_opentitan_synth
|
396 KB |
|
plots_tests_asan_read_systemverilog
|
220 KB |
|
plots_tests_asan_read_uhdm
|
166 KB |
|
plots_tests_plugin_read_systemverilog
|
35.8 KB |
|
plots_tests_plugin_read_uhdm
|
34.8 KB |
|
plots_tests_release_read_systemverilog
|
34.8 KB |
|
plots_tests_release_read_uhdm
|
32 KB |
|
plots_veer_synth
|
39.2 KB |
|
python_bp_e_bp_unicore_cfg.edif
|
3.9 MB |
|
results_parsing_tests_asan_read_systemverilog
Expired
|
1.64 MB |
|
results_parsing_tests_asan_read_uhdm
Expired
|
1.84 MB |
|
results_parsing_tests_plugin_read_systemverilog
Expired
|
1.51 MB |
|
results_parsing_tests_plugin_read_uhdm
Expired
|
1.76 MB |
|
results_parsing_tests_release_read_systemverilog
Expired
|
1.5 MB |
|
results_parsing_tests_release_read_uhdm
Expired
|
1.75 MB |
|
tools
|
38.9 MB |
|
top_artya7.bit
|
121 KB |
|