Refactor converting AST_DOT to range selects (#2629) #5998

Job	Run time
Build Synlig Release	5m 24s
Build Plugin	4m 27s
Build Synlig (ASAN)	9m 50s
Build Package	5m 5s
Build PySynlig	10m 59s
Build tools	10m 46s
Emit Workflow Info	0s
Style check	2m 37s
Verify README Correctness (Installation From Sources)	42m 46s
Formal Verification Tests / simple	17m 36s
Formal Verification Tests / sv2v	19m 31s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 34s
Large Designs Tests / Ibex (Vivado synthesis)	6m 21s
Formal Verification Tests / yosys	14m 25s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 46s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	35m 55s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 25s
Large Designs Tests / Opentitan parsing (full/top-down)	17m 48s
Large Designs Tests / Opentitan (synthesis)	1h 27m 18s
Large Designs Tests / Opentitan parsing (quick)	5m 55s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	49m 22s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 18s
Large Designs Tests / Black Parrot (ASIC synthesis)	44m 59s
Parsing Tests / Test read_systemverilog release	4m 35s
Parsing Tests / Test read_uhdm release	4m 37s
Parsing Tests / Test read_systemverilog plugin	4m 40s
Parsing Tests / Test read_uhdm plugin	4m 16s
Parsing Tests / Test read_systemverilog asan	35m 13s
Parsing Tests / Test read_uhdm asan	25m 10s
Parsing Tests / Summary Generation	1m 39s
Parsing Tests / Generate AST diff	1m 41s
Release Package	10s
Verify README Correctness (Download And Run Release)	1m 51s
	8h 34m 59s

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