Fix pushing logs to main branch of synlig-logs repo #5990

Job	Run time
Build Synlig Release	4m 17s
Build Plugin	3m 49s
Build Synlig (ASAN)	7m 55s
Emit Workflow Info	0s
Build Package	4m 43s
Build PySynlig	8m 52s
Style check	1m 31s
Build tools	10m 37s
Verify README Correctness (Installation From Sources)	43m 21s
Parsing Tests / Test read_systemverilog release	4m 31s
Parsing Tests / Test read_uhdm release	4m 14s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 46s
Large Designs Tests / Ibex (Vivado synthesis)	6m 17s
Parsing Tests / Test read_systemverilog plugin	4m 36s
Parsing Tests / Test read_uhdm plugin	4m 19s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 35s
Parsing Tests / Test read_systemverilog asan	35m 13s
Parsing Tests / Test read_uhdm asan	25m 24s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	35m 7s
Large Designs Tests / Opentitan parsing (full/top-down)	13m 11s
Large Designs Tests / Opentitan parsing (quick)	6m 31s
Large Designs Tests / Opentitan (synthesis)	1h 7m 38s
Large Designs Tests / Black Parrot (ASIC synthesis)	37m 7s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 48s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	41m 11s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 6s
Formal Verification Tests / simple	15m 23s
Formal Verification Tests / sv2v	15m 30s
Formal Verification Tests / yosys	14m 29s
Parsing Tests / Summary Generation	1m 28s
Parsing Tests / Generate AST diff	3m 2s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 40m 31s

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