Follow up fix for blackbox attribute #5987

Job	Run time
Style check	1m 29s
Build Synlig Release	4m 33s
Build Plugin	3m 38s
Build Synlig (ASAN)	7m 6s
Build tools	10m 35s
Emit Workflow Info	0s
Build Package	4m 30s
Verify README Correctness (Installation From Sources)	41m 47s
Build PySynlig	10m 20s
Large Designs Tests / Opentitan (synthesis)	49m 10s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	31m 19s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 18s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 19s
Large Designs Tests / Ibex (Vivado synthesis)	6m 21s
Large Designs Tests / Opentitan parsing (quick)	5m 47s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 33s
Large Designs Tests / Black Parrot (ASIC synthesis)	38m 40s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	32m 14s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 16s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	13m 13s
Parsing Tests / Test read_systemverilog release	4m 24s
Parsing Tests / Test read_uhdm release	4m 28s
Parsing Tests / Test read_systemverilog plugin	4m 29s
Parsing Tests / Test read_uhdm plugin	4m 11s
Parsing Tests / Test read_systemverilog asan	34m 43s
Parsing Tests / Test read_uhdm asan	25m 11s
Formal Verification Tests / simple	15m 45s
Formal Verification Tests / sv2v	17m 8s
Formal Verification Tests / yosys	11m 42s
Parsing Tests / Summary Generation	1m 36s
Parsing Tests / Generate AST diff	0s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	6h 59m 45s

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