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Build(deps): Bump third_party/sby from 117fb26 to daed0e1 #5979

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Build(deps): Bump third_party/sby from 117fb26 to daed0e1

Build(deps): Bump third_party/sby from 117fb26 to daed0e1 #5979

Run time

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Job Run time
Build Synlig Release
5m 46s
Build Synlig Release
1s
Build Synlig Release
20m 29s
Build tools
44s
Build tools
5m 54s
Build tools
12m 16s
Emit Workflow Info
0s
Emit Workflow Info
0s
Emit Workflow Info
0s
Build Plugin
44s
Build Plugin
5m 54s
Build Plugin
19m 24s
Build Synlig (ASAN)
5m 46s
Build Synlig (ASAN)
1s
Build Synlig (ASAN)
20m 30s
Build Package
5m 46s
Build Package
1s
Build Package
21m 1s
Style check
47s
Style check
5m 54s
Style check
1m 43s
Build PySynlig
5m 45s
Build PySynlig
1s
Build PySynlig
10m 25s
Verify README Correctness (Installation From Sources)
45s
Verify README Correctness (Installation From Sources)
5m 54s
Verify README Correctness (Installation From Sources)
41m 20s
Formal Verification Tests
0s
Formal Verification Tests
0s
Diff generated BSG Micro Designs tests
0s
Diff generated BSG Micro Designs tests
0s
Large Designs Tests
0s
Large Designs Tests
0s
Parsing Tests
0s
Parsing Tests
0s
Release Package
0s
Release Package
0s
Release Package
0s
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
0s
Formal Verification Tests / simple
17m 20s
Large Designs Tests / Ibex (Vivado synthesis)
6m 21s
Formal Verification Tests / sv2v
17m 12s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
38m 9s
Formal Verification Tests / yosys
11m 29s
Large Designs Tests / Ibex (F4PGA synthesis)
11m 17s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
14m 24s
Large Designs Tests / Opentitan parsing (full/top-down)
12m 17s
Large Designs Tests / Opentitan (synthesis)
50m 7s
Large Designs Tests / Opentitan parsing (quick)
5m 40s
Large Designs Tests / VeeR-EH1 (synthesis)
5m 2s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
6m 20s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
41m 15s
Parsing Tests / Test read_systemverilog release
4m 24s
Parsing Tests / Test read_uhdm release
5m 11s
Parsing Tests / Test read_systemverilog plugin
4m 20s
Parsing Tests / Test read_uhdm plugin
4m 14s
Parsing Tests / Test read_systemverilog asan
34m 40s
Parsing Tests / Test read_uhdm asan
25m 18s
Large Designs Tests / Black Parrot (ASIC synthesis)
37m 38s
Parsing Tests / Summary Generation
1m 31s
Parsing Tests / Generate AST diff
1m 36s
9h 12m 36s