Build(deps): Bump third_party/eqy from 7b16456 to d327440
#5910
Triggered via pull request
September 19, 2024 13:02
dependabot[bot]
Status
Success
Total duration
1h 17m 51s
Artifacts
42
main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 52s
Emit Workflow Info
0s
Style check
1m 24s
Verify README Correctness (Installation From Sources)
34m 47s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 14s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 17s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
27m 53s
Large Designs Tests
/
Opentitan (synthesis)
1h 9m
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 41s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
14m 16s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
46m 2s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 30s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 44s
Parsing Tests
/
Summary Generation
1m 42s
Verify README Correctness (Download And Run Release)
0s
Annotations
7 warnings
|
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
|
|
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
|
|
Formal Verification Tests / yosys
No files were found with the provided path: yosys_formal_verification_logs.tar. No artifacts will be uploaded.
|
|
Formal Verification Tests / sv2v
No files were found with the provided path: sv2v_formal_verification_logs.tar. No artifacts will be uploaded.
|
|
Formal Verification Tests / simple
No files were found with the provided path: simple_formal_verification_logs.tar. No artifacts will be uploaded.
|
|
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
|
|
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
|
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
binaries-asan
|
288 MB |
|
|
binaries-package
|
22.6 MB |
|
|
binaries-plugin
|
40.8 MB |
|
|
binaries-release
|
41.4 MB |
|
|
bp_e_bp_unicore_cfg.edif
|
3.9 MB |
|
|
bsg-logs
|
5.47 MB |
|
|
bsg-outputs
|
1.72 MB |
|
|
lowrisc_ibex_top_artya7_surelog_0.1.bit
|
107 KB |
|
|
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
612 KB |
|
|
opentitan-logs-full
|
5.08 MB |
|
|
opentitan-logs-quick
|
1.52 MB |
|
|
plots_binaries-asan
|
52.1 KB |
|
|
plots_binaries-package
|
30.4 KB |
|
|
plots_binaries-plugin
|
31.8 KB |
|
|
plots_binaries-release
|
36.5 KB |
|
|
plots_blackparrot_synth_asic
|
240 KB |
|
|
plots_blackparrot_synth_xilinx
|
92.3 KB |
|
|
plots_build_tools
|
81.7 KB |
|
|
plots_formal_verification_simple
|
99.4 KB |
|
|
plots_formal_verification_sv2v
|
100 KB |
|
|
plots_formal_verification_yosys
|
87.2 KB |
|
|
plots_ibex_synth
|
44.2 KB |
|
|
plots_ibex_synth_f4pga
|
80.2 KB |
|
|
plots_opentitan_9d82960888_synth
|
151 KB |
|
|
plots_opentitan_parse_report_full
|
80.3 KB |
|
|
plots_opentitan_parse_report_quick
|
42 KB |
|
|
plots_opentitan_synth
|
345 KB |
|
|
plots_tests_asan_read_systemverilog
|
212 KB |
|
|
plots_tests_asan_read_uhdm
|
156 KB |
|
|
plots_tests_plugin_read_systemverilog
|
35.4 KB |
|
|
plots_tests_plugin_read_uhdm
|
33.5 KB |
|
|
plots_tests_release_read_systemverilog
|
34.6 KB |
|
|
plots_tests_release_read_uhdm
|
32.6 KB |
|
|
plots_veer_synth
|
37.8 KB |
|
|
results_parsing_tests_asan_read_systemverilog
Expired
|
390 KB |
|
|
results_parsing_tests_asan_read_uhdm
Expired
|
1.82 MB |
|
|
results_parsing_tests_plugin_read_systemverilog
Expired
|
256 KB |
|
|
results_parsing_tests_plugin_read_uhdm
Expired
|
1.72 MB |
|
|
results_parsing_tests_release_read_systemverilog
Expired
|
255 KB |
|
|
results_parsing_tests_release_read_uhdm
Expired
|
1.7 MB |
|
|
tools
|
38.9 MB |
|
|
top_artya7.bit
|
121 KB |
|