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Build(deps): Bump third_party/ibex from 87dfd07 to 6a33f69 #5902

Build(deps): Bump third_party/ibex from 87dfd07 to 6a33f69

Build(deps): Bump third_party/ibex from 87dfd07 to 6a33f69 #5902

Triggered via pull request September 19, 2024 07:23
Status Failure
Total duration 1h 0m 21s
Artifacts 38

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 43s
Style check
Verify README Correctness (Installation From Sources)
41m 22s
Verify README Correctness (Installation From Sources)
Parsing Tests  /  SystemVerilog Plugin
40m 55s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
2m 46s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
5m 44s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
30m 10s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
52m 6s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 8s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 20s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
34m 25s
Large Designs Tests / Black Parrot (ASIC synthesis)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 35s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
5m 18s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 16s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

2 errors and 5 warnings
Large Designs Tests / Ibex (Vivado synthesis)
Process completed with exit code 2.
Large Designs Tests / Ibex (F4PGA synthesis)
Process completed with exit code 2.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
Deprecation notice: v1, v2, and v3 of the artifact actions
The following artifacts were uploaded using a version of actions/upload-artifact that is scheduled for deprecation: "parsing_read-systemverilog_logs", "parsing_read-systemverilog_yosys-sv", "parsing_read-uhdm_logs", "parsing_read-uhdm_yosys-sv", "parsing_test-results", "plots_tests_read_systemverilog", "plots_tests_read_uhdm". Please update your workflow to use v4 of the artifact actions. Learn more: https://github.blog/changelog/2024-04-16-deprecation-notice-v3-of-the-artifact-actions/

Artifacts

Produced during runtime
Name Size
binaries-asan
288 MB
binaries-package
22.6 MB
binaries-plugin
40.8 MB
binaries-release
41.4 MB
bp_e_bp_unicore_cfg.edif
3.9 MB
bsg-logs
5.47 MB
bsg-outputs
1.72 MB
formal-verification-logs-simple
141 MB
formal-verification-logs-sv2v
161 MB
formal-verification-logs-yosys
157 MB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
612 KB
opentitan-logs-full
5.09 MB
opentitan-logs-quick
1.52 MB
parsing_read-systemverilog_logs
82.8 KB
parsing_read-systemverilog_yosys-sv
348 KB
parsing_read-uhdm_logs
16 MB
parsing_read-uhdm_yosys-sv
345 KB
parsing_test-results Expired
23.7 KB
plots_binaries-asan
52.9 KB
plots_binaries-package
31.5 KB
plots_binaries-plugin
30.3 KB
plots_binaries-release
31.8 KB
plots_blackparrot_synth_asic
204 KB
plots_blackparrot_synth_xilinx
106 KB
plots_build_tools
78.4 KB
plots_formal_verification_simple
99.3 KB
plots_formal_verification_sv2v
102 KB
plots_formal_verification_yosys
86 KB
plots_ibex_synth
19.7 KB
plots_ibex_synth_f4pga
44 KB
plots_opentitan_9d82960888_synth
162 KB
plots_opentitan_parse_report_full
88.8 KB
plots_opentitan_parse_report_quick
41.4 KB
plots_opentitan_synth
261 KB
plots_tests_read_systemverilog
2.4 MB
plots_tests_read_uhdm
1.93 MB
plots_veer_synth
35.5 KB
tools
38.9 MB