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Refactor parsing tests CI #5901

Refactor parsing tests CI

Refactor parsing tests CI #5901

Triggered via pull request September 18, 2024 13:13
Status Success
Total duration 1h 5m 12s
Artifacts 45

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 27s
Style check
Verify README Correctness (Installation From Sources)
36m 17s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 13s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
10m 49s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
28m 42s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
57m 9s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 23s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
13m 0s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
36m 12s
Large Designs Tests / Black Parrot (ASIC synthesis)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 11s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 49s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 40s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

4 warnings
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
288 MB
binaries-package
22.6 MB
binaries-plugin
40.9 MB
binaries-release
41.4 MB
bp_e_bp_unicore_cfg.edif
3.9 MB
bsg-logs
5.47 MB
bsg-outputs
1.72 MB
formal-verification-logs-simple
149 MB
formal-verification-logs-sv2v
168 MB
formal-verification-logs-yosys
154 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
107 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
612 KB
opentitan-logs-full
5.1 MB
opentitan-logs-quick
1.52 MB
plots_binaries-asan
49.9 KB
plots_binaries-package
30.3 KB
plots_binaries-plugin
29.8 KB
plots_binaries-release
29.6 KB
plots_blackparrot_synth_asic
210 KB
plots_blackparrot_synth_xilinx
85.4 KB
plots_build_tools
78.6 KB
plots_formal_verification_simple
103 KB
plots_formal_verification_sv2v
96.8 KB
plots_formal_verification_yosys
88.1 KB
plots_ibex_synth
42.6 KB
plots_ibex_synth_f4pga
76.4 KB
plots_opentitan_9d82960888_synth
155 KB
plots_opentitan_parse_report_full
82.4 KB
plots_opentitan_parse_report_quick
44.8 KB
plots_opentitan_synth
290 KB
plots_tests_asan_read_systemverilog
214 KB
plots_tests_asan_read_uhdm
160 KB
plots_tests_plugin_read_systemverilog
36.2 KB
plots_tests_plugin_read_uhdm
33.3 KB
plots_tests_release_read_systemverilog
35.1 KB
plots_tests_release_read_uhdm
32.9 KB
plots_veer_synth
35.5 KB
results_parsing_tests_asan_read_systemverilog Expired
389 KB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
256 KB
results_parsing_tests_plugin_read_uhdm Expired
1.72 MB
results_parsing_tests_release_read_systemverilog Expired
255 KB
results_parsing_tests_release_read_uhdm Expired
1.7 MB
tools
38.9 MB
top_artya7.bit
121 KB