Change format of release package (#2558) #5869
tgorochowikmain.yml
on: push
Matrix: build-binaries
Build tools
12m 32s
Emit Workflow Info
0s
Style check
1m 59s
Test "Installation from source" from README
34m 3s
Upload GHA event file
3s
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 24s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 9s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
30m 1s
Large Designs Tests
/
Opentitan (synthesis)
1h 7m
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 43s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
14m 10s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
37m 37s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 42s
Test With Bundled Yosys
3m 11s
Matrix: Formal Verification Tests / tests-formal-verification
Release Package
16s
Annotations
7 warnings
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Release Package
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Release Package
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/checkout@v2, 8BitJonny/[email protected]. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/
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Deprecation notice: v1, v2, and v3 of the artifact actions
The following artifacts were uploaded using a version of actions/upload-artifact that is scheduled for deprecation: "parsing_read-systemverilog_logs", "parsing_read-systemverilog_yosys-sv", "parsing_read-uhdm_logs", "parsing_read-uhdm_yosys-sv", "parsing_test-results", "plots_tests_read_systemverilog", "plots_tests_read_uhdm".
Please update your workflow to use v4 of the artifact actions.
Learn more: https://github.blog/changelog/2024-04-16-deprecation-notice-v3-of-the-artifact-actions/
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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binaries-asan
|
288 MB |
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binaries-package
|
22.6 MB |
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binaries-plugin
|
40.9 MB |
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binaries-release
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41.4 MB |
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bp_e_bp_unicore_cfg.edif
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3.9 MB |
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bsg-logs
|
5.47 MB |
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bsg-outputs
|
1.72 MB |
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event.json
|
2.54 KB |
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formal-verification-logs-simple
|
150 MB |
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formal-verification-logs-sv2v
|
162 MB |
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formal-verification-logs-yosys
|
156 MB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
|
107 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
612 KB |
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opentitan-logs-full
|
5.08 MB |
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opentitan-logs-quick
|
1.52 MB |
|
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opentitan-synlig.ast
|
132 MB |
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parsing_read-systemverilog_logs
|
16.1 MB |
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parsing_read-systemverilog_yosys-sv
|
350 KB |
|
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parsing_read-uhdm_logs
|
16.1 MB |
|
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parsing_read-uhdm_yosys-sv
|
348 KB |
|
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parsing_test-results
Expired
|
23.7 KB |
|
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plots_binaries-asan
|
49.6 KB |
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plots_binaries-package
|
33.1 KB |
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plots_binaries-plugin
|
30.6 KB |
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plots_binaries-release
|
38.5 KB |
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plots_blackparrot_synth_asic
|
204 KB |
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plots_blackparrot_synth_xilinx
|
90.3 KB |
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plots_build_tools
|
90.2 KB |
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plots_formal_verification_simple
|
106 KB |
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plots_formal_verification_sv2v
|
106 KB |
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plots_formal_verification_yosys
|
86.8 KB |
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plots_ibex_synth
|
44.5 KB |
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plots_ibex_synth_f4pga
|
78 KB |
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plots_opentitan_9d82960888_synth
|
166 KB |
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plots_opentitan_parse_report_full
|
97.6 KB |
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plots_opentitan_parse_report_quick
|
48.2 KB |
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plots_opentitan_synth
|
346 KB |
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plots_tests_read_systemverilog
|
2.43 MB |
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plots_tests_read_uhdm
|
1.91 MB |
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plots_veer_synth
|
37.8 KB |
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tools
|
38.9 MB |
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top_artya7.bit
|
121 KB |
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