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Bump upload-artifact and download-artifact versions #5867

Bump upload-artifact and download-artifact versions

Bump upload-artifact and download-artifact versions #5867

Triggered via pull request September 12, 2024 10:41
Status Success
Total duration 1h 36m 56s
Artifacts 41

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 59s
Style check
Test "Installation from source" from README
34m 5s
Test "Installation from source" from README
Upload GHA event file
12s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
41m 30s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 30s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 20s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
35m 22s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
1h 23m
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 7s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 26s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
46m 38s
Large Designs Tests / Black Parrot (ASIC synthesis)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 45s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Test With Bundled Yosys
3m 6s
Test With Bundled Yosys
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
4m 59s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 24s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
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Annotations

5 warnings
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
Deprecation notice: v1, v2, and v3 of the artifact actions
The following artifacts were uploaded using a version of actions/upload-artifact that is scheduled for deprecation: "parsing_read-systemverilog_logs", "parsing_read-systemverilog_yosys-sv", "parsing_read-uhdm_logs", "parsing_read-uhdm_yosys-sv", "parsing_test-results", "plots_tests_read_systemverilog", "plots_tests_read_uhdm". Please update your workflow to use v4 of the artifact actions. Learn more: https://github.blog/changelog/2024-04-16-deprecation-notice-v3-of-the-artifact-actions/

Artifacts

Produced during runtime
Name Size
binaries-asan
288 MB
binaries-package
22.6 MB
binaries-plugin
40.8 MB
binaries-release
41.4 MB
bp_e_bp_unicore_cfg.edif
3.9 MB
bsg-logs
5.47 MB
bsg-outputs
1.72 MB
event.json
3.25 KB
formal-verification-logs-simple
143 MB
formal-verification-logs-sv2v
165 MB
formal-verification-logs-yosys
161 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
107 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
612 KB
opentitan-logs-full
5.09 MB
opentitan-logs-quick
1.52 MB
parsing_read-systemverilog_logs
16.1 MB
parsing_read-systemverilog_yosys-sv
350 KB
parsing_read-uhdm_logs
16.1 MB
parsing_read-uhdm_yosys-sv
348 KB
parsing_test-results Expired
23.7 KB
plots_binaries-asan
55 KB
plots_binaries-package
32.7 KB
plots_binaries-plugin
31.7 KB
plots_binaries-release
31.2 KB
plots_blackparrot_synth_asic
253 KB
plots_blackparrot_synth_xilinx
106 KB
plots_build_tools
79.7 KB
plots_formal_verification_simple
116 KB
plots_formal_verification_sv2v
119 KB
plots_formal_verification_yosys
98 KB
plots_ibex_synth
44.5 KB
plots_ibex_synth_f4pga
79.1 KB
plots_opentitan_9d82960888_synth
190 KB
plots_opentitan_parse_report_full
98.6 KB
plots_opentitan_parse_report_quick
47 KB
plots_opentitan_synth
422 KB
plots_tests_read_systemverilog
2.45 MB
plots_tests_read_uhdm
1.91 MB
plots_veer_synth
35.5 KB
tools
38.9 MB
top_artya7.bit
121 KB