Fail CI on every result difference #5858

Job	Run time
Emit Workflow Info	0s
Build Synlig Release	5m 23s
Style check	2m 4s
Build Plugin	5m 23s
Build tools	11m 9s
Build Synlig (ASAN)	8m 44s
Test "Installation from source" from README	35m 30s
Upload GHA event file	1s
Test With Bundled Yosys	3m 4s
Parsing Tests / SystemVerilog Plugin	41m 31s
Parsing Tests / Surelog	31m 17s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	9m 40s
Large Designs Tests / Ibex (Vivado synthesis)	6m 1s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 26s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	29m 0s
Large Designs Tests / Opentitan parsing (full/top-down)	16m 26s
Large Designs Tests / Opentitan parsing (quick)	9m 15s
Large Designs Tests / Opentitan (synthesis)	57m 6s
Large Designs Tests / Black Parrot (ASIC synthesis)	38m 16s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	14m 10s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 34s
Formal Verification Tests / simple	16m 12s
Formal Verification Tests / sv2v	15m 19s
Formal Verification Tests / yosys	12m 52s
Parsing Tests / Summary Generation	1m 48s
Parsing Tests / Generate AST diff	4m 48s
Release Package	0s
	6h 31m 59s

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