Setup Github release and enable systemwide installation #5855
kamilrakoczymain.yml
on: pull_request
Matrix: build-binaries
Build tools
12m 4s
Emit Workflow Info
0s
Style check
1m 40s
Test "Installation from source" from README
28m 13s
Upload GHA event file
4s
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests
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Ibex (Vivado synthesis)
6m 28s
Large Designs Tests
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Ibex (F4PGA synthesis)
7m 37s
Large Designs Tests
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Opentitan 9d82960888 (synthesis)
7m 25s
Large Designs Tests
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Opentitan (synthesis)
7m 27s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 15s
Large Designs Tests
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Black Parrot (AMD (Xilinx) FPGA synthesis)
7m 20s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
7m 23s
Diff generated BSG Micro Designs tests
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Parse and diff BSG Micro Designs
2m 38s
Test With Bundled Yosys
3m 7s
Matrix: Formal Verification Tests / tests-formal-verification
Waiting for pending jobs
Release Package
0s
Annotations
23 errors and 5 warnings
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Build tools
Process completed with exit code 2.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Process completed with exit code 1.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Process completed with exit code 1.
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Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
The operation was canceled.
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Large Designs Tests / Black Parrot (ASIC synthesis)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Black Parrot (ASIC synthesis)
The operation was canceled.
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Large Designs Tests / Opentitan 9d82960888 (synthesis)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Opentitan 9d82960888 (synthesis)
The operation was canceled.
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Large Designs Tests / Opentitan (synthesis)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Opentitan (synthesis)
The operation was canceled.
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Test "Installation from source" from README
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Test "Installation from source" from README
The operation was canceled.
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Large Designs Tests / Ibex (F4PGA synthesis)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Ibex (F4PGA synthesis)
The operation was canceled.
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Large Designs Tests / Opentitan parsing (full/top-down)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Opentitan parsing (full/top-down)
The operation was canceled.
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Parsing Tests / SystemVerilog Plugin
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Parsing Tests / SystemVerilog Plugin
The operation was canceled.
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Parsing Tests / Surelog
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Parsing Tests / Surelog
The operation was canceled.
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Large Designs Tests / Opentitan parsing (quick)
Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/pull/2552/merge' exists
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Large Designs Tests / Opentitan parsing (quick)
The operation was canceled.
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Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Upload GHA event file
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.
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Deprecation notice: v1, v2, and v3 of the artifact actions
The following artifacts were uploaded using a version of actions/upload-artifact that is scheduled for deprecation: "binaries-asan", "binaries-package", "binaries-plugin", "binaries-release", "event.json", "lowrisc_ibex_top_artya7_surelog_0.1.bit", "parsing_read-systemverilog_logs", "parsing_read-systemverilog_yosys-sv", "parsing_read-uhdm_logs", "parsing_read-uhdm_yosys-sv", "parsing_test-results", "plots".
Please update your workflow to use v4 of the artifact actions.
Learn more: https://github.blog/changelog/2024-04-16-deprecation-notice-v3-of-the-artifact-actions/
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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binaries-asan
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1.02 GB |
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binaries-package
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68.7 MB |
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binaries-plugin
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139 MB |
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binaries-release
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139 MB |
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event.json
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28.2 KB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
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2.09 MB |
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parsing_read-systemverilog_logs
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1.26 MB |
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parsing_read-systemverilog_yosys-sv
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34 KB |
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parsing_read-uhdm_logs
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2.08 MB |
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parsing_read-uhdm_yosys-sv
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35 KB |
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parsing_test-results
Expired
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3.16 KB |
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plots
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8.3 MB |
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