Expose additional recovery signals to the top-level

src/csr/I3CCSR.sv

@@ -4741,8 +4741,8 @@ module I3CCSR (
         automatic logic load_next_c;
         next_c = field_storage.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.value;
         load_next_c = '0;
-        if(decoded_reg_strb.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL && decoded_req_is_wr) begin // SW write
-            next_c = (field_storage.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+        if(decoded_reg_strb.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL && decoded_req_is_wr) begin // SW write 1 clear
+            next_c = field_storage.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.value & ~(decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
             load_next_c = '1;
         end else if(hwif_in.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.we) begin // HW Write - we
             next_c = hwif_in.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.next;
@@ -4759,6 +4759,7 @@ module I3CCSR (
         end
     end
     assign hwif_out.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.value = field_storage.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.value;
+    assign hwif_out.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL.PLACEHOLDER.swmod = decoded_reg_strb.I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL && decoded_req_is_wr;
     // Field: I3CCSR.I3C_EC.SecFwRecoveryIf.RECOVERY_STATUS.PLACEHOLDER
     always_comb begin
         automatic logic [31:0] next_c;
@@ -5023,6 +5024,8 @@ module I3CCSR (
         end
     end
     assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.PLACEHOLDER.value = field_storage.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.PLACEHOLDER.value;
+    assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.PLACEHOLDER.swmod = decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA && decoded_req_is_wr;
+    assign hwif_out.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA.PLACEHOLDER.swacc = decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA;
     assign hwif_out.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER.CAP_ID.value = 8'h12;
     assign hwif_out.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER.CAP_LENGTH.value = 16'h10;
     // Field: I3CCSR.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.PENDING_RX_NACK

src/csr/I3CCSR_pkg.sv

@@ -1764,6 +1764,7 @@ package I3CCSR_pkg;
 
     typedef struct packed{
         logic [31:0] value;
+        logic swmod;
     } I3CCSR__I3C_EC__SecFwRecoveryIf__RECOVERY_CTRL__PLACEHOLDER__out_t;
 
     typedef struct packed{
@@ -1852,6 +1853,8 @@ package I3CCSR_pkg;
 
     typedef struct packed{
         logic [31:0] value;
+        logic swmod;
+        logic swacc;
     } I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_DATA__PLACEHOLDER__out_t;
 
     typedef struct packed{

src/csr/I3CCSR_uvm.sv

@@ -2224,7 +2224,7 @@ package I3CCSR_uvm;
 
         virtual function void build();
             this.PLACEHOLDER = new("PLACEHOLDER");
-            this.PLACEHOLDER.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            this.PLACEHOLDER.configure(this, 32, 0, "W1C", 1, 'h0, 1, 1, 0);
             if (has_coverage(UVM_CVR_REG_BITS)) begin
                 foreach(PLACEHOLDER_bit_cg[bt]) PLACEHOLDER_bit_cg[bt] = new();
             end

src/i3c.sv

@@ -174,7 +174,11 @@ module i3c
 
     // DCT memory export interface
     input  dct_mem_src_t  dct_mem_src_i,
-    output dct_mem_sink_t dct_mem_sink_o
+    output dct_mem_sink_t dct_mem_sink_o,
+
+    // Recovery interface signals
+    output logic recovery_payload_available_o,
+    output logic recovery_image_activated_o
 
     // TODO: Add interrupts
 );
@@ -962,6 +966,10 @@ module i3c
 
       .irq_o(),  // TODO: Connect me
 
+      // Recovery status signals
+      .payload_available_o (recovery_payload_available_o),
+      .image_activated_o   (recovery_image_activated_o),
+
       // I2C/I3C bus condition detection
       .ctl_bus_start_i(bus_start | bus_rstart),  // S/Sr are both used to reset PEC
       .ctl_bus_stop_i (bus_stop),

src/i3c_wrapper.sv

@@ -99,13 +99,17 @@ module i3c_wrapper #(
     input  logic sda_i,
     output logic scl_o,
     output logic sda_o,
-    output logic sel_od_pp_o
+    output logic sel_od_pp_o,
 `else
     // I3C bus IO
     inout  wire  i3c_scl_io,
-    inout  wire  i3c_sda_io
+    inout  wire  i3c_sda_io,
 `endif
 
+    // Recovery interface signals
+    output logic recovery_payload_available_o,
+    output logic recovery_image_activated_o
+
     // TODO: Add interrupts
 );
 
@@ -259,7 +263,10 @@ module i3c_wrapper #(
       .dat_mem_sink_o(dat_mem_sink),
 
       .dct_mem_src_i (dct_mem_src),
-      .dct_mem_sink_o(dct_mem_sink)
+      .dct_mem_sink_o(dct_mem_sink),
+
+      .recovery_payload_available_o (recovery_payload_available_o),
+      .recovery_image_activated_o   (recovery_image_activated_o)
   );
 
   prim_ram_1p_adv #(

src/rdl/docs/README.md

@@ -1335,9 +1335,9 @@ When set to 0, it holds execution of enqueued commands and runs current command
 - Base Offset: 0x3C
 - Size: 0x4
 
-|Bits| Identifier|Access|Reset|Name|
-|----|-----------|------|-----|----|
-|31:0|PLACEHOLDER|  rw  | 0x0 |    |
+|Bits| Identifier|  Access |Reset|Name|
+|----|-----------|---------|-----|----|
+|31:0|PLACEHOLDER|rw, woclr| 0x0 |    |
 
 #### PLACEHOLDER field
 

src/rdl/secure_firmware_recovery_interface.rdl

@@ -184,6 +184,8 @@ regfile SecureFirmwareRecoveryInterfaceRegisters{
             hw = rw;
             we = true;
             reset = 32'h00000000;
+            onwrite = woclr;
+            swmod = true;
         } PLACEHOLDER[31:0];
     } RECOVERY_CTRL;
     reg {
@@ -305,6 +307,8 @@ regfile SecureFirmwareRecoveryInterfaceRegisters{
             hw = rw;
             we = true;
             reset = 32'h00000000;
+            swacc = true;
+            swmod = true;
         } PLACEHOLDER[31:0];
     } INDIRECT_FIFO_DATA;
 };

src/recovery/recovery_executor.sv

@@ -42,6 +42,10 @@ module recovery_executor
 
     input logic host_abort_i,
 
+    // Recovery status signals
+    output logic payload_available_o,
+    output logic image_activated_o,
+
     // Recovery CSR interface
     input  I3CCSR_pkg::I3CCSR__I3C_EC__SecFwRecoveryIf__out_t hwif_rec_i,
     output I3CCSR_pkg::I3CCSR__I3C_EC__SecFwRecoveryIf__in_t  hwif_rec_o
@@ -113,6 +117,7 @@ module recovery_executor
   logic [31:0] csr_data;
   logic [15:0] csr_length;
   logic        csr_writeable;
+  logic        csr_ff_data;
 
   // ....................................................
 
@@ -247,6 +252,11 @@ module recovery_executor
       default: csr_length <= csr_length;
     endcase
 
+  // Set high if the command targets CMD_INDIRECT_FIFO_DATA and is a write.
+  always_ff @(posedge clk_i)
+    if ((state_q == Idle) && cmd_valid_i)
+        csr_ff_data <= (cmd_cmd_i == CMD_INDIRECT_FIFO_DATA) && !cmd_is_rd_i;
+
   // CSR read data mux (registered)
   always_ff @(posedge clk_i)
     unique case (csr_sel)
@@ -406,4 +416,25 @@ module recovery_executor
       default:     res_dlast_o <= '0;
     endcase
 
+  // ....................................................
+
+  // Payload availability logic
+  // Assety payload_available_o upon reception of a complete recovery write
+  // packet targeting CSR_INDIRECT_FIFO_DATA.
+  always_ff @(posedge clk_i or negedge rst_ni)
+    if (!rst_ni)
+      payload_available_o <= '0;
+    else begin
+      // "Execution" (reception) of a INDIRECT_FIFO_DATA write command complete
+      if ((state_q == Done) && csr_ff_data)
+        payload_available_o <= 1'b1;
+      // Read of INDIRECT_FIFO_DATA from HCI side.
+      if (hwif_rec_i.INDIRECT_FIFO_DATA.PLACEHOLDER.swacc &&
+          !hwif_rec_i.INDIRECT_FIFO_DATA.PLACEHOLDER.swmod)
+        payload_available_o <= 1'b0;
+    end
+
+  // Image activation logic.
+  assign image_activated_o = (hwif_rec_i.RECOVERY_CTRL.PLACEHOLDER.value[23:16] == 8'h0F);
+
 endmodule

src/recovery/recovery_handler.sv

@@ -156,7 +156,11 @@ module recovery_handler
     // ....................................................
 
     // Interrupt
-    output logic irq_o
+    output logic irq_o,
+
+    // Recovery status
+    output logic payload_available_o,
+    output logic image_activated_o
 );
 
   // ....................................................
@@ -395,6 +399,9 @@ module recovery_handler
       .tx_reg_rst_data_o(tti_tx_data_queue_reg_rst_next)
   );
 
+  // Recovery data available signal.
+  assign payload_available_o = recovery_enable & !tti_rx_data_queue_empty;
+
   // IBI
   write_queue #(
 
@@ -506,14 +513,15 @@ module recovery_handler
   logic [7:0] recv_tti_rx_data_data;
 
   logic       recv_tti_rx_data_queue_select;
+  logic       recv_tti_rx_data_queue_flush;
   logic       recv_tti_rx_data_queue_flow;
 
   // RX data queue
   always_comb begin : R2MUX
     if (recovery_enable & recv_tti_rx_data_queue_select) begin
       recv_tti_rx_data_valid                  = ctl_tti_rx_data_queue_wvalid_i;
       tti_rx_data_queue_wvalid                = '0;
-      tti_rx_data_queue_wflush                = '0;
+      tti_rx_data_queue_wflush                = recv_tti_rx_data_queue_flush;
       ctl_tti_rx_data_queue_full_o            = tti_rx_data_queue_full;
       ctl_tti_rx_data_queue_empty_o           = tti_rx_data_queue_empty;
       ctl_tti_rx_data_queue_wready_o          = recv_tti_rx_data_ready;
@@ -749,6 +757,7 @@ module recovery_handler
       .data_data_i (recv_tti_rx_data_data),
 
       .data_queue_select_o(recv_tti_rx_data_queue_select),
+      .data_queue_flush_o (recv_tti_rx_data_queue_flush),
       .data_queue_flow_i  (tti_rx_data_queue_wvalid & tti_rx_data_queue_wready),
 
       .bus_start_i(ctl_bus_start_i),
@@ -867,6 +876,9 @@ module recovery_handler
 
       .host_abort_i(ctl_tti_tx_host_nack_i | ctl_bus_stop_i),
 
+      .payload_available_o (payload_available_o),
+      .image_activated_o (image_activated_o),
+
       .hwif_rec_i(hwif_rec_i),
       .hwif_rec_o(hwif_rec_o)
   );

src/recovery/recovery_receiver.sv

@@ -19,6 +19,7 @@ module recovery_receiver
 
     // TTI RX data queue mux control and data flow monitor
     output logic data_queue_select_o,
+    output logic data_queue_flush_o,
     input  logic data_queue_flow_i,
 
     // Bus condition detection
@@ -131,6 +132,11 @@ module recovery_receiver
     if (!rst_ni) data_queue_select_o <= 1'b1;
     else if (state_q == RxData) data_queue_select_o <= (data_queue_flow_i & dcnt == 1);
 
+  // Data queue flush signal. Flush if data length is not divisible by 4
+  always_ff @(posedge clk_i)
+    if (!rst_ni) data_queue_flush_o <= 1'b0;
+    else data_queue_flush_o <= (state_q == Cmd) && |(len_lsb[1:0]);
+
   // Data counter
   always_ff @(posedge clk_i)
     unique case (state_q)