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Fixes to recovery read
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Signed-off-by: Michal Czyz <[email protected]>
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@mczyz-antmicro
mczyz-antmicro committed Oct 11, 2024
1 parent 780b386 commit ca22726
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Showing 25 changed files with 319 additions and 336 deletions.
33 changes: 17 additions & 16 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -51,15 +51,16 @@ CFG_GEN = $(TOOL_DIR)/i3c_config/i3c_core_config.py

config: config-rtl config-rdl ## Generate RDL and RTL configuration files

PYTHON ?= python3
config-rtl: config-print ## Generate top I3C definitions svh file
python $(CFG_GEN) $(CFG_NAME) $(CFG_FILE) svh_file --output-file $(SRC_DIR)/i3c_defines.svh
$(PYTHON) $(CFG_GEN) $(CFG_NAME) $(CFG_FILE) svh_file --output-file $(SRC_DIR)/i3c_defines.svh

RDL_REGS := $(SRC_DIR)/rdl/registers.rdl
RDL_GEN_DIR := $(SRC_DIR)/csr/
RDL_ARGS := $(shell python $(CFG_GEN) $(CFG_NAME) $(CFG_FILE) reg_gen_opts)
RDL_ARGS := $(shell $(PYTHON) $(CFG_GEN) $(CFG_NAME) $(CFG_FILE) reg_gen_opts)

config-rdl: config-print
python $(TOOL_DIR)/reg_gen/reg_gen.py --input-file=$(RDL_REGS) --output-dir=$(RDL_GEN_DIR) $(RDL_ARGS) $(EXTRA_REG_GEN_ARGS)
$(PYTHON) $(TOOL_DIR)/reg_gen/reg_gen.py --input-file=$(RDL_REGS) --output-dir=$(RDL_GEN_DIR) $(RDL_ARGS) $(EXTRA_REG_GEN_ARGS)

config-print: ## Print configuration name, filename and RDL arguments
@echo Using \'$(CFG_NAME)\' I3C configuration from \'$(CFG_FILE)\'.
Expand All @@ -71,57 +72,57 @@ config-print: ## Print configuration name, filename and RDL arguments
lint: lint-rtl lint-tests ## Run RTL and tests lint

lint-check: lint-rtl ## Run RTL lint and check lint on tests source code without fixing errors
cd $(COCOTB_VERIF_DIR) && python -m nox -R -s test_lint
cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -s test_lint

lint-rtl: ## Run lint on RTL source code
$(SHELL) $(TOOL_DIR)/verible-scripts/run.sh

lint-tests: ## Run lint on tests source code
cd $(COCOTB_VERIF_DIR) && python -m nox -R -s lint
cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -s lint

#
# Tests
#
test: config ## Run single module test (use `TEST=<test_name>` flag)
cd $(COCOTB_VERIF_DIR) && python -m nox -R -s $(TEST)_verify
cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -s $(TEST)_verify

tests-axi: ## Run all verification/cocotb/* RTL tests for AXI bus configuration without coverage
$(MAKE) config CFG_NAME=axi
cd $(COCOTB_VERIF_DIR) && python -m nox -R -t "axi"
cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -t "axi"

tests-ahb: ## Run all verification/cocotb/* RTL tests for AHB bus configuration without coverage
$(MAKE) config CFG_NAME=ahb
cd $(COCOTB_VERIF_DIR) && python -m nox -R -t "ahb"
cd $(COCOTB_VERIF_DIR) && $(PYTHON) -m nox -R -t "ahb"

tests: tests-axi tests-ahb ## Run all verification/cocotb/* RTL tests fro AHB and AXI bus configurations without coverage

# TODO: Enable full coverage flow
tests-coverage: ## Run all verification/block/* RTL tests with coverage
cd $(COCOTB_VERIF_DIR) && BLOCK_COVERAGE_ENABLE=1 python -m nox -R -k "verify"
cd $(COCOTB_VERIF_DIR) && BLOCK_COVERAGE_ENABLE=1 $(PYTHON) -m nox -R -k "verify"

test-i3c-vip-uvm: config ## Run single I3C VIP UVM test with nox (use 'TEST=<i3c_driver|i3c_monitor>' flag)
cd $(UVM_VERIF_DIR) && python -m nox -R -s $(TEST)
cd $(UVM_VERIF_DIR) && $(PYTHON) -m nox -R -s $(TEST)

tests-i3c-vip-uvm: config ## Run all I3C VIP UVM tests with nox
cd $(UVM_VERIF_DIR) && python -m nox -R -s "i3c_verify_uvm"
cd $(UVM_VERIF_DIR) && $(PYTHON) -m nox -R -s "i3c_verify_uvm"

tests-i3c-vip-uvm-debug: config ## Run debugging I3C VIP UVM tests with nox
cd $(UVM_VERIF_DIR) && python -m nox -R -t "uvm_debug_tests"
cd $(UVM_VERIF_DIR) && $(PYTHON) -m nox -R -t "uvm_debug_tests"

tests-uvm: config ## Run all I3C Core UVM tests with nox
cd $(UVM_VERIF_DIR) && python -m nox -R -s "i3c_core_verify_uvm"
cd $(UVM_VERIF_DIR) && $(PYTHON) -m nox -R -s "i3c_core_verify_uvm"

tests-uvm-debug: config ## Run debugging I3C Core UVM tests with nox
cd $(UVM_VERIF_DIR) && python -m nox -R -s "i3c_core_uvm_debug_tests"
cd $(UVM_VERIF_DIR) && $(PYTHON) -m nox -R -s "i3c_core_uvm_debug_tests"

tests-tool: ## Run all tool tests
cd $(TOOL_VERIF_DIR) && python -m nox -k "verify"
cd $(TOOL_VERIF_DIR) && $(PYTHON) -m nox -k "verify"

#
# Utilities
#
timings: ## Generate values for I2C/I3C timings
python $(TOOL_DIR)/timing/timing.py
$(PYTHON) $(TOOL_DIR)/timing/timing.py

deps: ## Install python dependencies
pip install -r $(I3C_ROOT_DIR)/requirements.txt
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2 changes: 1 addition & 1 deletion i3c_core_configs.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -30,4 +30,4 @@ axi:
FrontendBusAddrWidth: 12
FrontendBusDataWidth: 32
FrontendBusUserWidth: 32
FrontendBusIdWidth: 2
FrontendBusIdWidth: 8
18 changes: 10 additions & 8 deletions src/ctrl/bus_monitor.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -29,9 +29,9 @@ module bus_monitor
output logic start_detect_o, // Module detected START or REPEATED START condition
output logic stop_detect_o, // Module detected STOP condition

input is_in_hdr_mode_i, // Module is in HDR mode
output hdr_exit_detect_o // Detected HDR exit condition (see: 5.2.1.1.1 of the base spec)
);
input is_in_hdr_mode_i, // Module is in HDR mode
output hdr_exit_detect_o // Detected HDR exit condition (see: 5.2.1.1.1 of the base spec)
);
logic enable, enable_q;

logic scl_negedge_i;
Expand Down Expand Up @@ -65,8 +65,9 @@ module bus_monitor

assign enable = enable_i;

edge_detector #(.DETECT_NEGEDGE(1'b1))
edge_detector_scl_negedge (
edge_detector #(
.DETECT_NEGEDGE(1'b1)
) edge_detector_scl_negedge (
.clk_i(clk_i),
.rst_ni(rst_ni),
.trigger(scl_negedge_i),
Expand All @@ -84,8 +85,9 @@ module bus_monitor
.detect(scl_posedge)
);

edge_detector #(.DETECT_NEGEDGE(1'b1))
edge_detector_sda_negedge (
edge_detector #(
.DETECT_NEGEDGE(1'b1)
) edge_detector_sda_negedge (
.clk_i(clk_i),
.rst_ni(rst_ni),
.trigger(sda_negedge_i),
Expand Down Expand Up @@ -204,7 +206,7 @@ module bus_monitor
end else if (hdr_exit_det_trigger) begin
hdr_exit_det_pending <= 1'b1;
end else if (!enable || stop_det) begin
hdr_exit_det_count <= 5'b10000;
hdr_exit_det_count <= 5'b10000;
hdr_exit_det_pending <= 1'b0;
end else if (enable && hdr_exit_det_pending && sda_negedge) begin
hdr_exit_det_count <= {1'b0, hdr_exit_det_count[4:1]};
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12 changes: 6 additions & 6 deletions src/ctrl/ccc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -37,13 +37,14 @@ module ccc
logic [7:0] defining_byte;
logic defining_byte_valid;
logic [7:0] command_data;
logic clear_command_code;

always_ff @(posedge clk_i or negedge rst_ni) begin : proc_latch_inputs
if (~rst_ni) begin
command_code <= '0;
command_code <= '0;
defining_byte <= '0;
defining_byte_valid <= '0;
command_data <= '0;
command_data <= '0;
end else begin
if (clear_command_code) begin
command_code <= '0;
Expand All @@ -52,7 +53,7 @@ module ccc
end
defining_byte <= defining_byte_valid_i ? defining_byte_i : defining_byte;
defining_byte_valid <= defining_byte_valid_i;
command_data <= command_data_valid_i ? command_data_i : command_data;
command_data <= command_data_valid_i ? command_data_i : command_data;
end
end

Expand All @@ -70,12 +71,11 @@ module ccc
// Decode CCC
logic is_direct_cmd = command_code[7]; // 0 - BCast, 1 - Direct

// CCC handling logic
logic clear_command_code;


always_comb begin
response_valid_o = '0;
response_byte_o = '0;
response_byte_o = '0;
enter_hdr_ccc_o = '0;
rst_action_o = '0;
command_min_bytes_o = '0;
Expand Down
2 changes: 1 addition & 1 deletion src/ctrl/controller_standby.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -200,7 +200,7 @@ module controller_standby
.rx_queue_wvalid_o(i2c_rx_queue_wvalid_o),
.rx_queue_wready_i(rx_queue_wready_i),
.rx_queue_wdata_o(i2c_rx_queue_wdata_o),
// .rx_queue_wflush_o(i2c_rx_queue_wflush_o), // TODO: Add flush support for I2C
// .rx_queue_wflush_o(i2c_rx_queue_wflush_o), // TODO: Add flush support for I2C
.tx_queue_full_i(tx_queue_full_i),
.tx_queue_start_thld_i(tx_queue_start_thld_i),
.tx_queue_start_thld_trig_i(tx_queue_start_thld_trig_i),
Expand Down
4 changes: 2 additions & 2 deletions src/ctrl/controller_standby_i2c.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -191,8 +191,8 @@ module controller_standby_i2c

// TODO: Make the I2C FSM report start/stop condition detection
assign bus_start_o = '0;
assign bus_rstart_o= '0;
assign bus_stop_o = '0;
assign bus_rstart_o = '0;
assign bus_stop_o = '0;

// TODO: Make the I2C FSM output its received address + RnW bit and connect
// them here.
Expand Down
2 changes: 1 addition & 1 deletion src/ctrl/edge_detector.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ module edge_detector
end else if (trigger) begin
check_in_progress <= 1'b1;
count <= '0;
end else if(check_in_progress && detect_line) begin
end else if (check_in_progress && detect_line) begin
count <= count + 1'b1;
if (count >= delay_count) begin
check_in_progress <= 1'b0;
Expand Down
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