Merge branch 'main' into dev/george/svsim

README.md

@@ -55,7 +55,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt
 [![Join the chat at https://gitter.im/freechipsproject/chisel3](https://badges.gitter.im/chipsalliance/chisel3.svg)](https://gitter.im/freechipsproject/chisel3?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 ![CI](https://github.com/chipsalliance/chisel3/actions/workflows/test.yml/badge.svg)
 [![GitHub tag (latest SemVer)](https://img.shields.io/github/v/tag/chipsalliance/chisel3.svg?include_prereleases&sort=semver)](https://github.com/chipsalliance/chisel3/releases/latest)
-[![Scala version support](https://index.scala-lang.org/chipsalliance/chisel3/chisel3/latest-by-scala-version.svg?color=blue)](https://index.scala-lang.org/chipsalliance/chisel3/chisel3)
+[![chisel3 Scala version support](https://index.scala-lang.org/chipsalliance/chisel/chisel3/latest-by-scala-version.svg?platform=jvm)](https://index.scala-lang.org/chipsalliance/chisel/chisel3)
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 [![Scaladoc](https://www.javadoc.io/badge/edu.berkeley.cs/chisel3_2.13.svg?color=blue&label=Scaladoc)](https://javadoc.io/doc/edu.berkeley.cs/chisel3_2.13/latest)
 

firrtl/src/main/scala/firrtl/ir/Serializer.scala

@@ -65,7 +65,7 @@ object Serializer {
       case n: Circuit   => sIt(n)(indent)
       case other => Iterator(serialize(other, indent))
     }
-  }
+  }.view // TODO replace .view with constructing a view directly above, but must drop 2.12 first.
 
   private def flattenInfo(infos: Seq[Info]): Seq[FileInfo] = infos.flatMap {
     case NoInfo => Seq()

firrtl/src/test/scala/firrtlTests/SerializerSpec.scala

@@ -176,4 +176,38 @@ class SerializerSpec extends AnyFlatSpec with Matchers {
     SMemTestCircuit.circuit(ReadUnderWrite.New).serialize should include("new")
     SMemTestCircuit.circuit(ReadUnderWrite.Old).serialize should include("old")
   }
+
+  it should "support lazy serialization" in {
+    var stmtSerialized = false
+    case class HackStmt(stmt: Statement) extends Statement {
+      def serialize: String = {
+        stmtSerialized = true
+        stmt.serialize
+      }
+    }
+
+    val stmt = HackStmt(DefNode(NoInfo, "foo", Reference("bar")))
+    val it: Iterable[String] = Serializer.lazily(stmt)
+    assert(!stmtSerialized, "We should be able to construct the serializer lazily")
+
+    var mapExecuted = false
+    val it2: Iterable[String] = it.map { x =>
+      mapExecuted = true
+      x + ","
+    }
+    assert(!stmtSerialized && !mapExecuted, "We should be able to map the serializer lazily")
+
+    var appendExecuted = false
+    val it3: Iterable[String] = it2 ++ Seq("hi").view.map { x =>
+      appendExecuted = true
+      x
+    }
+    assert(!stmtSerialized && !mapExecuted && !appendExecuted, "We should be able to append to the serializer lazily")
+
+    val result = it3.mkString
+    assert(
+      stmtSerialized && mapExecuted && appendExecuted,
+      "Once we traverse the serializer, everything should execute"
+    )
+  }
 }