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chipsalliance · Mar 7, 2024 · 149c75c · 149c75c
1 parent 51c49d1
commit 149c75c
Showing 1 changed file with 6 additions and 5 deletions.
diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala
@@ -3,7 +3,8 @@
 package gcd
 
 import chisel3._
-import circt.stage.ChiselStage
+// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
+import _root_.circt.stage.ChiselStage
 
 /**
   * Compute GCD using subtraction method.
@@ -38,8 +39,8 @@ class GCD extends Module {
  * Generate Verilog sources and save it in file GCD.v
  */
 object GCD extends App {
-  val verilog_src = ChiselStage.emitSystemVerilogFile(
-      new GCD(),
-      firtoolOpts = Array("-disable-all-randomization",
-                          "-strip-debug-info"))
+  ChiselStage.emitSystemVerilogFile(
+    new GCD,
+    firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
+  )
 }