Sync cell replacement in Caliptra

[DerekWangScaleflux]

Hi,
I'm trying to replace sync cell in Caliptra with technology specific standard cells.

Is there a list of all the sync cell used ?

Also, I'm seeing places which is using the following RTL to sync, for example:
rvtop.dmi_wrapper.i_dmi_jtag_to_core_sync.rden[2:0]

 Will it get updated to use standard cells ?

Best Regards
Derek Wang

[nstewart-amd]

The VeeR dmi_jtag_to_core_sync issue is captured here:
chipsalliance/Cores-VeeR-EL2#51

[nstewart-amd]

@DerekWangScaleflux - Please clarify what you mean by 'Is there a list of all the sync cell used ?'
Do you mean "which src files are modified to insert/replace with per-integrator specific sync cells"?

[nstewart-amd]

@DerekWangScaleflux

We replace the contents of these with our "integrator specific" sync module.

libs/rtl/caliptra_2ff_sync.sv
caliptra_prim/rtl/caliptra_prim_flop_2sync.sv

[steven-bellock]

@nstewart-amd I think he's asking how you handle

caliptra-rtl/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v

Line 25 in e181daf

module dmi_jtag_to_core_sync (

since that module includes both RTL synchronizer and read/write enable logic.

[nstewart-amd]

@nstewart-amd I think he's asking how you handle

caliptra-rtl/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v

Line 25 in e181daf

module dmi_jtag_to_core_sync (

since that module includes both RTL synchronizer and read/write enable logic.

@steven-bellock
The VeeR dmi jtag syncrhonizer is captured here:
chipsalliance/Cores-VeeR-EL2#51

As you've noted, it's "all RTL" currently and does not refer to an integrator replaced/replaceable module.
Accordingly, this module will need to "waived" or modified to replace the inferred flops with user synchronizer module.

[nstewart-amd]

See also here: #333

[DerekWangScaleflux]

Hi，
I have replace with specific cells in the following file:
(1) libs/rtl/caliptra_2ff_sync.sv
(2) caliptra_prim/rtl/caliptra_prim_flop_2sync.sv

•  Regarding to the sync logic in the following file, will there be any updates ?
  
     (1)  caliptra-rtl/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v
  

•  And the logic in el2_dbg ( line 277 ):
  

Its comments says "synchronize the rst", but why rst_l is connected to din ? It doesn't looks like a standard reset synchronizer.

•  Beside the previsous mentioned ones, are there other places need to replaced ?
  

Best Regards
Derek Wang