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Merge pull request #3782 from alainmarcel/master
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Rsd design typespec fix
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@alaindargelas
alaindargelas authored Jul 29, 2023
2 parents 343d800 + f0bfdd2 commit cd74fce
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Showing 36 changed files with 1,040 additions and 513 deletions.
5 changes: 3 additions & 2 deletions include/Surelog/DesignCompile/CompileFileContent.h
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Original file line number Diff line number Diff line change
Expand Up @@ -57,10 +57,10 @@ struct FunctorCompileFileContent {
class CompileFileContent final {
public:
CompileFileContent(CompileDesign* compiler, FileContent* file,
[[maybe_unused]] Design* design,
Design* design,
[[maybe_unused]] SymbolTable* symbols,
[[maybe_unused]] ErrorContainer* errors)
: m_compileDesign(compiler), m_fileContent(file) {
: m_compileDesign(compiler), m_fileContent(file), m_design(design) {
m_helper.seterrorReporting(errors, symbols);
}

Expand All @@ -72,6 +72,7 @@ class CompileFileContent final {
bool collectObjects_();
CompileDesign* const m_compileDesign;
FileContent* const m_fileContent;
Design* const m_design;

CompileHelper m_helper;
};
Expand Down
5 changes: 3 additions & 2 deletions src/DesignCompile/CompileDesign.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -311,8 +311,6 @@ bool CompileDesign::compilation_() {
compileMT_<FileContent, Design::FileIdDesignContentMap, FunctorResolve>(
all_files, maxThreadCount);

compileMT_<FileContent, Design::FileIdDesignContentMap,
FunctorCompileFileContent>(all_files, maxThreadCount);
collectObjects_(all_files, design, false);
m_compiler->getDesign()->orderPackages();

Expand All @@ -323,6 +321,9 @@ bool CompileDesign::compilation_() {
funct.operator()();
}

compileMT_<FileContent, Design::FileIdDesignContentMap,
FunctorCompileFileContent>(all_files, maxThreadCount);

// Compile modules
compileMT_<ModuleDefinition, ModuleNameModuleDefinitionMap,
FunctorCompileModule>(
Expand Down
4 changes: 4 additions & 0 deletions src/DesignCompile/CompileFileContent.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,10 @@ bool CompileFileContent::collectObjects_() {
VObjectType type = fC->Type(id);
switch (type) {
case VObjectType::slPackage_import_item: {
m_helper.importPackage(m_fileContent, m_design, fC, id,
m_compileDesign);
m_helper.compileImportDeclaration(m_fileContent, fC, id,
m_compileDesign);
FileCNodeId fnid(fC, id);
m_fileContent->addObject(type, fnid);
break;
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153 changes: 85 additions & 68 deletions src/DesignCompile/UhdmWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2313,13 +2313,15 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod,
tps = n->Typespec();
break;
}
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
found = true;
tps = n->Typespec();
break;
if (m) {
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
found = true;
tps = n->Typespec();
break;
}
}
}
}
Expand Down Expand Up @@ -2362,13 +2364,15 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod,
tps = n->Typespec();
break;
}
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
found = true;
tps = n->Typespec();
break;
if (m) {
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
found = true;
tps = n->Typespec();
break;
}
}
}
}
Expand Down Expand Up @@ -2448,32 +2452,34 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod,
}
}
if (found) break;
VectorOfport* ports = m->Ports();
if (ports) {
for (auto port : *ports) {
if (port->VpiName() == name) {
if (typespec* tmp = port->Typespec()) {
found = true;
tps = tmp;
break;
if (m) {
VectorOfport* ports = m->Ports();
if (ports) {
for (auto port : *ports) {
if (port->VpiName() == name) {
if (typespec* tmp = port->Typespec()) {
found = true;
tps = tmp;
break;
}
}
}
}
}
if (found) break;
VectorOfnet* nets = m->Nets();
if (nets) {
for (auto net : *nets) {
if (net->VpiName() == name) {
if (typespec* tmp = net->Typespec()) {
found = true;
tps = tmp;
break;
if (found) break;
VectorOfnet* nets = m->Nets();
if (nets) {
for (auto net : *nets) {
if (net->VpiName() == name) {
if (typespec* tmp = net->Typespec()) {
found = true;
tps = tmp;
break;
}
}
}
}
if (found) break;
}
if (found) break;
} else if (parent->UhdmType() == uhdmbegin) {
begin* b = (begin*)parent;
if (auto vars = b->Variables()) {
Expand Down Expand Up @@ -2815,12 +2821,15 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
ref->Actual_group(n);
break;
}
const std::string pname = StrCat(m->VpiName(), "::", typeName);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
if (m) {
const std::string pname =
StrCat(m->VpiName(), "::", typeName);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
}
}
}
}
Expand All @@ -2832,12 +2841,15 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
ref->Actual_group(n);
break;
}
const std::string pname = StrCat(m->VpiName(), "::", typeName);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
if (m) {
const std::string pname =
StrCat(m->VpiName(), "::", typeName);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
}
}
}
}
Expand Down Expand Up @@ -2902,12 +2914,14 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
ref->Actual_group(n);
break;
}
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
if (m) {
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
}
}
}
}
Expand Down Expand Up @@ -2947,12 +2961,14 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
ref->Actual_group(n);
break;
}
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
if (m) {
const std::string pname = StrCat(m->VpiName(), "::", name);
if (n->VpiName() == pname) {
if (n->UhdmType() == uhdmref_var) continue;
if (n->UhdmType() == uhdmref_obj) continue;
ref->Actual_group(n);
break;
}
}
}
}
Expand Down Expand Up @@ -3142,7 +3158,7 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
parent = parent->VpiParent();
}
if (ref->Actual_group()) continue;
if (m->UhdmType() == uhdmmodule_inst) {
if (m && (m->UhdmType() == uhdmmodule_inst)) {
module_inst* minst = (module_inst*)m;
if (minst->Interfaces()) {
for (auto n : *minst->Interfaces()) {
Expand All @@ -3163,8 +3179,9 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
if (ref->Actual_group()) continue;
}
}
if (m->UhdmType() == uhdmmodule_inst ||
m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram) {
if (m &&
(m->UhdmType() == uhdmmodule_inst ||
m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram)) {
instance* inst = (instance*)m;
if (inst->Nets()) {
for (auto n : *inst->Nets()) {
Expand All @@ -3185,7 +3202,7 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
if (ref->Actual_group()) continue;
}
}
if (m->Variables()) {
if (m && m->Variables()) {
for (auto n : *m->Variables()) {
if (n->VpiName() == name) {
ref->Actual_group(n);
Expand All @@ -3200,7 +3217,7 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
if (ref->Actual_group()) continue;
}

if (m->Param_assigns()) {
if (m && m->Param_assigns()) {
bool isParam = false;
for (auto p : *m->Param_assigns()) {
const any* lhs = p->Lhs();
Expand All @@ -3213,7 +3230,7 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
}
if (isParam) continue;
}
if (m->Parameters()) {
if (m && m->Parameters()) {
bool isParam = false;
for (auto p : *m->Parameters()) {
if (p->VpiName() == name) {
Expand All @@ -3224,7 +3241,7 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
if (isParam) continue;
}

if (m->Typespecs()) {
if (m && m->Typespecs()) {
bool isTypespec = false;
std::vector<std::string> importedPackages;
for (auto n : *m->Typespecs()) {
Expand Down Expand Up @@ -3283,7 +3300,7 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
if (ref->Actual_group()) break;
}

if (m->Variables()) {
if (m && m->Variables()) {
for (auto var : *m->Variables()) {
if (var->UhdmType() == uhdmenum_var) {
const enum_typespec* tps =
Expand Down Expand Up @@ -3318,9 +3335,9 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
->getCommandLineParser()
->muteStdout());
} else {
if (m->UhdmType() == uhdmmodule_inst ||
m->UhdmType() == uhdminterface_inst ||
m->UhdmType() == uhdmprogram) {
if (m && (m->UhdmType() == uhdmmodule_inst ||
m->UhdmType() == uhdminterface_inst ||
m->UhdmType() == uhdmprogram)) {
instance* inst = (instance*)m;
logic_net* net = s.MakeLogic_net();
net->VpiName(name);
Expand Down
32 changes: 29 additions & 3 deletions tests/BitsLogic/BitsLogic.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -202,8 +202,9 @@ AST_DEBUG_END
[INF:UH0706] Creating UHDM Model...

=== UHDM Object Stats Begin (Non-Elaborated Model) ===
constant 21
constant 22
design 1
import_typespec 1
int_typespec 2
logic_net 1
logic_typespec 7
Expand All @@ -222,8 +223,9 @@ typespec_member 6
[INF:UH0707] Elaborating UHDM...

=== UHDM Object Stats Begin (Elaborated Model) ===
constant 21
constant 22
design 1
import_typespec 1
int_typespec 2
logic_net 1
logic_typespec 7
Expand Down Expand Up @@ -260,7 +262,7 @@ design: (work@top)
|vpiTypedef:
\_struct_typespec: (SchedulerTypes::IntIssueQueueEntry), line:3:9, endln:6:2
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10
\_package: SchedulerTypes (SchedulerTypes::), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:1:1, endln:8:11
|vpiName:SchedulerTypes::IntIssueQueueEntry
|vpiInstance:
\_package: SchedulerTypes (SchedulerTypes::), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:1:1, endln:8:11
Expand Down Expand Up @@ -290,6 +292,28 @@ design: (work@top)
|vpiFullName:SchedulerTypes::
|vpiTypedef:
\_struct_typespec: (SchedulerTypes::IntIssueQueueEntry), line:3:9, endln:6:2
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10
|vpiName:SchedulerTypes::IntIssueQueueEntry
|vpiInstance:
\_package: SchedulerTypes (SchedulerTypes::), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:1:1, endln:8:11
|vpiPacked:1
|vpiTypespecMember:
\_typespec_member: (a), line:5:11, endln:5:12
|vpiParent:
\_struct_typespec: (SchedulerTypes::IntIssueQueueEntry), line:3:9, endln:6:2
|vpiName:a
|vpiTypespec:
\_logic_typespec: , line:5:5, endln:5:10
|vpiParent:
\_typespec_member: (a), line:5:11, endln:5:12
|vpiInstance:
\_package: SchedulerTypes (SchedulerTypes::), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:1:1, endln:8:11
|vpiRefFile:${SURELOG_DIR}/tests/BitsLogic/dut.sv
|vpiRefLineNo:5
|vpiRefColumnNo:5
|vpiRefEndLineNo:5
|vpiRefEndColumnNo:10
|vpiDefName:SchedulerTypes
|vpiTop:1
|uhdmallModules:
Expand Down Expand Up @@ -510,6 +534,8 @@ design: (work@top)
|vpiName:b
|vpiFullName:[email protected]
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (SchedulerTypes::IntIssueQueueEntry), line:3:9, endln:6:2
|uhdmtopModules:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsLogic/dut.sv, line:12:1, endln:28:10
|vpiName:work@top
Expand Down
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