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alaindargelas committed Oct 14, 2023
1 parent 85dc2c6 commit 8ce307a
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Showing 2 changed files with 26 additions and 16 deletions.
2 changes: 1 addition & 1 deletion third_party/tests/CoresSweRVMP/CoresSweRVMP.log
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
CMake that the project does not need compatibility with older versions.


-- Configuring done (0.1s)
-- Configuring done (0.0s)
-- Generating done (0.0s)
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
[ 6%] Generating 10_lsu_bus_intf.sv
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40 changes: 25 additions & 15 deletions third_party/tests/SimpleUVM/SimpleUVM.log
Original file line number Diff line number Diff line change
Expand Up @@ -386,8 +386,8 @@ assign_stmt 3547
assignment 6293
begin 6779
bit_select 2126
bit_typespec 3074
bit_var 1194
bit_typespec 3078
bit_var 1196
break_stmt 53
byte_typespec 120
byte_var 38
Expand All @@ -398,9 +398,9 @@ chandle_var 2
class_defn 615
class_typespec 8549
class_var 3294
clocking_block 1
clocking_io_decl 4
constant 28556
clocking_block 3
clocking_io_decl 12
constant 28592
constraint 4
continue_stmt 52
delay_control 54
Expand All @@ -410,7 +410,7 @@ do_while 51
enum_const 551
enum_typespec 93
enum_var 186
event_control 17
event_control 19
event_stmt 10
event_typespec 10
extends 279
Expand All @@ -430,32 +430,32 @@ indexed_part_select 41
initial 3
int_typespec 2767
int_var 1363
interface_inst 1
interface_inst 5
interface_typespec 1
io_decl 6908
logic_net 238
logic_typespec 93
logic_net 246
logic_typespec 109
logic_var 49
long_int_typespec 99
long_int_var 20
method_func_call 8000
module_inst 32
module_inst 34
named_begin 6
named_event 8
named_fork 3
operation 10002
operation 10004
package 4
packed_array_typespec 8
param_assign 468
parameter 673
part_select 43
port 16
range 2896
port 26
range 2914
real_typespec 33
real_var 8
ref_module 1
ref_obj 41208
ref_typespec 20760
ref_obj 41230
ref_typespec 20780
ref_var 1788
repeat 27
return_stmt 3272
Expand Down Expand Up @@ -3907,6 +3907,16 @@ while_stmt 108
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/testbench.sv:61:7: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_misc.svh:74:39: Non synthesizable construct, $urandom
[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_misc.svh:74:39: Non synthesizable construct, $urandom
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:33:15: Non synthesizable construct, a
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:34:15: Non synthesizable construct, b
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:35:15: Non synthesizable construct, doAdd
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:36:15: Non synthesizable construct, result
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:32:3: Non synthesizable construct, cb
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:33:15: Non synthesizable construct, a
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:34:15: Non synthesizable construct, b
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:35:15: Non synthesizable construct, doAdd
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:36:15: Non synthesizable construct, result
[LINT]: ${SURELOG_DIR}/third_party/tests/SimpleUVM/design.sv:32:3: Non synthesizable construct, cb
[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_agent.svh:67:6: Unsupported typespec, uvm_resource_types::rsrc_q_t
[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/macros/uvm_resource_defines.svh:123:6: Unsupported typespec, __tmp_int_t__
[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_traversal.svh:168:13: Unsupported typespec, c
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