double loop unique scope

src/Design/ModuleInstance.cpp

@@ -304,14 +304,25 @@ void ModuleInstance::overrideParentChild(ModuleInstance* parent,
   Netlist* netlist = interm->getNetlist();
   if (netlist) {
     if (netlist->cont_assigns() || netlist->process_stmts() ||
-        netlist->array_nets() || netlist->array_vars() ||
-        netlist->param_assigns() || netlist->nets() || netlist->variables() ||
+        netlist->array_nets() || netlist->param_assigns() ||
+        netlist->array_vars() || netlist->nets() || netlist->variables() ||
         netlist->interface_arrays() || netlist->interfaces())
       return;
   }
 
-  // Loop indexes
   Netlist* child_netlist = child->getNetlist();
+  if (netlist->param_assigns()) {
+    auto params = child_netlist->param_assigns();
+    if (params == nullptr) {
+      params = s.MakeParam_assignVec();
+    }
+    child_netlist->param_assigns(params);
+    for (auto p : *netlist->param_assigns()) {
+      params->push_back(p);
+    }
+  }
+
+  // Loop indexes
   for (auto& param : interm->getMappedValues()) {
     const std::string_view name = param.first;
     Value* val = param.second.first;

src/DesignCompile/DesignElaboration.cpp

@@ -2512,6 +2512,7 @@ void DesignElaboration::reduceUnnamedBlocks_() {
            typeP == VObjectType::paLoop_generate_construct ||
            typeP == VObjectType::paGenerate_module_loop_statement ||
            typeP == VObjectType::paGenerate_interface_loop_statement ||
+           typeP == VObjectType::paGenerate_begin_end_block ||
            typeP == VObjectType::paGenerate_region ||
            typeP == VObjectType::paGenerate_item)) {
         std::string_view fullModName =
@@ -2522,16 +2523,22 @@ void DesignElaboration::reduceUnnamedBlocks_() {
           parent->getParent()->overrideParentChild(parent->getParent(), parent,
                                                    current, s);
         } else if (fullModName.find("genblk") != std::string::npos) {
-          if (fullModName == fullModNameP)
-            parent->getParent()->overrideParentChild(parent->getParent(),
-                                                     parent, current, s);
+          if (fullModName == fullModNameP) {
+            if (fullModNameP.find("[") == std::string::npos) {
+              parent->getParent()->overrideParentChild(parent->getParent(),
+                                                       parent, current, s);
+            }
+          }
         } else {
           if (type == VObjectType::paGenerate_item &&
               typeP == VObjectType::paGenerate_item) {
           } else {
-            if (fullModNameP.find("genblk") != std::string::npos)
-              parent->getParent()->overrideParentChild(parent->getParent(),
-                                                       parent, current, s);
+            if (fullModNameP.find("genblk") != std::string::npos) {
+              if (fullModNameP.find("[") == std::string::npos) {
+                parent->getParent()->overrideParentChild(parent->getParent(),
+                                                         parent, current, s);
+              }
+            }
           }
         }
       }

tests/DoubleLoop/dut.sv

@@ -1,5 +1,5 @@
 
-module constpower(ys, yu);
+module constpower1(ys, yu);
 
 output [2:0] ys, yu;
 
@@ -16,45 +16,73 @@ endgenerate
 
 endmodule
 
-/*
+module constpower2(ys, yu);
 
-interface rggen_register_if #(
-);
- 
-
-  logic                     valid;
-  logic [31:0]   value;
+output [2:0] ys, yu;
 
-  modport register (
-    input   valid,
-    output  value
-  );
+genvar i, j;
 
-  modport monitor (
-    input valid,
-    input value
-  );
-endinterface
+generate
+	for (i = 0; i < 2; i = i+1) 
+	for (j = 0; j < 2; j = j+1) begin
+		assign ys= i + j;
+
+	end
 
+endgenerate
 
-module rggen_bit_field (input logic [31:0] o_value);
 endmodule
 
-module top();
-  rggen_register_if  register_if[1]();
+module constpower3(ys, yu);
+
+output [2:0] ys, yu;
+
+genvar i, j;
 
+generate
+	for (i = 0; i < 2; i = i+1) begin
+	for (j = 0; j < 2; j = j+1) 
+		assign ys= i + j;
+
+	end
 
-  // assign o = register_if[0].value[8+:1];
-  
-  rggen_bit_field i1 (
-    .o_value            (register_if)
-  );
+endgenerate
 
-   rggen_bit_field  u_bit_field (
-    .o_value            (register_if[0].value[8+:1])
-  );
-  
+endmodule // constpower3
 
-endmodule
+module constpower4(ys, yu);
+
+output [2:0] ys, yu;
+
+genvar i, j;
+
+generate
+	for (i = 0; i < 2; i = i+1) begin
+	for (j = 0; j < 2; j = j+1) begin
+		assign ys= i + j;
+
+	end
+        end
+
+endgenerate
+
+endmodule // constpower4
+
+
+module constpower5(ys, yu);
+
+output [2:0] ys, yu;
+
+genvar i, j;
+
+generate
+	for (i = 0; i < 2; i = i+1) 
+	for (j = 0; j < 2; j = j+1) 
+		assign ys= i + j;
+
+
+
+
+endgenerate
 
-*/
+endmodule // constpower5

third_party/tests/CoresSweRVMP/CoresSweRVMP.log

@@ -134,22 +134,22 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
 -- Configuring done (0.0s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[  6%] Generating 11_ifu_bp_ctl.sv
+[  6%] Generating 10_lsu_bus_intf.sv
 [ 12%] Generating 12_beh_lib.sv
-[ 18%] Generating 13_ifu_mem_ctl.sv
-[ 25%] Generating 10_lsu_bus_intf.sv
+[ 18%] Generating 11_ifu_bp_ctl.sv
+[ 25%] Generating 13_ifu_mem_ctl.sv
 [ 31%] Generating 14_mem_lib.sv
 [ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
-[ 50%] Generating 2_ahb_to_axi4.sv
-[ 56%] Generating 1_lsu_stbuf.sv
+[ 50%] Generating 1_lsu_stbuf.sv
+[ 56%] Generating 2_ahb_to_axi4.sv
 [ 62%] Generating 3_rvjtag_tap.sv
 [ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
 [ 87%] Generating 7_axi4_to_ahb.sv
-[ 93%] Generating 9_tb_top.sv
-[100%] Generating 8_ifu_aln_ctl.sv
+[ 93%] Generating 8_ifu_aln_ctl.sv
+[100%] Generating 9_tb_top.sv
 [100%] Built target Parse
 Surelog parsing status: 0
 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".