export DMI signals

design/dmi/dmi_mux.v

@@ -3,6 +3,8 @@
 
 module dmi_mux (
 
+    // Core access enable
+    input wire core_enable,
     // Uncore access enable
     input wire uncore_enable,
 
@@ -33,8 +35,8 @@ module dmi_mux (
   assign is_uncore_aperture = (dmi_addr[6] & (dmi_addr[5] | dmi_addr[4]));
 
   // Core signals
-  assign dmi_core_en        = dmi_en & ~is_uncore_aperture;
-  assign dmi_core_wr_en     = dmi_wr_en & ~is_uncore_aperture;
+  assign dmi_core_en        = dmi_en & ~is_uncore_aperture & core_enable;
+  assign dmi_core_wr_en     = dmi_wr_en & ~is_uncore_aperture & core_enable;
   assign dmi_core_addr      = dmi_addr;
   assign dmi_core_wdata     = dmi_wdata;
 

design/el2_veer_wrapper.sv

@@ -375,7 +375,7 @@
    output logic                            dma_hreadyout,
    output logic                            dma_hresp,
 `endif
    // clk ratio signals
    input logic                             lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
    input logic                             ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
    input logic                             dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
@@ -435,12 +435,14 @@
    input logic                             mbist_mode,    // to enable mbist
 
    // DMI port for uncore
+   input logic                             dmi_core_enable,
    input logic                             dmi_uncore_enable,
    output logic                            dmi_uncore_en,
    output logic                            dmi_uncore_wr_en,
    output logic                     [ 6:0] dmi_uncore_addr,
    output logic                     [31:0] dmi_uncore_wdata,
-   input logic                      [31:0] dmi_uncore_rdata
+   input logic                      [31:0] dmi_uncore_rdata,
+   output logic                            dmi_active
    /* verilator coverage_on */
 );
 
@@ -604,7 +606,7 @@
 
 
 `ifdef RV_BUILD_AHB_LITE
    // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
    /*verilator coverage_off*/
    wire                            lsu_axi_awvalid;
    wire                            lsu_axi_awready;
@@ -907,6 +909,7 @@
 
    // DMI core/uncore mux
    dmi_mux dmi_mux (
+    .core_enable        (dmi_core_enable),
     .uncore_enable      (dmi_uncore_enable),
 
     .dmi_en             (dmi_en),
@@ -928,6 +931,8 @@
     .dmi_uncore_rdata   (dmi_uncore_rdata)
    );
 
+   always_comb dmi_active = dmi_en;
+
 `ifdef RV_ASSERT_ON
   // to avoid internal assertions failure at time 0
   initial begin

testbench/tb_top.sv

@@ -156,6 +156,10 @@ module tb_top
     logic [11:0]                wb_csr_dest;
     logic [31:0]                wb_csr_data;
 
+    logic dmi_core_enable;
+
+    always_comb dmi_core_enable = ~(o_cpu_halt_status);
+
    `ifdef RV_OPENOCD_TEST
     // SB and LSU AHB master mux
     ahb_lite_2to1_mux #(
@@ -1302,12 +1306,14 @@ veer_wrapper rvtop_wrapper (
     .scan_mode              ( 1'b0 ),         // To enable scan mode
     .mbist_mode             ( 1'b0 ),        // to enable mbist
 
+    .dmi_core_enable        (dmi_core_enable),
     .dmi_uncore_enable      (),
     .dmi_uncore_en          (),
     .dmi_uncore_wr_en       (),
     .dmi_uncore_addr        (),
     .dmi_uncore_wdata       (),
-    .dmi_uncore_rdata       ()
+    .dmi_uncore_rdata       (),
+    .dmi_active             ()
 
 );
 

testbench/veer_wrapper.sv

@@ -350,13 +350,16 @@ module veer_wrapper
     input logic scan_mode,  // To enable scan mode
     input logic mbist_mode,  // to enable mbist
 
+    input  logic        dmi_core_enable,
     // DMI port for uncore
     input  logic        dmi_uncore_enable,
     output logic        dmi_uncore_en,
     output logic        dmi_uncore_wr_en,
     output logic [ 6:0] dmi_uncore_addr,
     output logic [31:0] dmi_uncore_wdata,
-    input  logic [31:0] dmi_uncore_rdata
+    input  logic [31:0] dmi_uncore_rdata,
+
+    output logic        dmi_active
 );
 
   el2_mem_if mem_export ();
@@ -378,6 +381,8 @@ module veer_wrapper
 
   el2_veer_wrapper rvtop (
       .el2_mem_export(mem_export.veer_sram_src),
+      .dmi_core_enable(dmi_core_enable),
+      .dmi_active(dmi_active),
       .*
   );
 

verification/block/dmi/dmi_test_wrapper.sv

@@ -49,6 +49,9 @@ module dmi_test_wrapper
   logic [ 6:0] dmi_addr;
   logic [31:0] dmi_wdata;
   logic [31:0] dmi_rdata;
+  logic        core_enable;
+
+  assign core_enable = '1;
 
   assign dmi_en = reg_en;
   assign dmi_wr_en = reg_wr_en;