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export DMI signals #259

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export DMI signals #259

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@wsipak wsipak commented Nov 7, 2024

This PR aims to resolve #257

input logic [31:0] dmi_uncore_rdata
input logic [31:0] dmi_uncore_rdata,

output logic dmi_active
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
output logic dmi_active
output logic dmi_active

… access

This integrates changes from caliptra-rtl:
chipsalliance/caliptra-rtl@22c08e1

Signed-off-by: Wojciech Sipak <[email protected]>
This integrates changes from caliptra-rtl:
chipsalliance/caliptra-rtl@4117344

Signed-off-by: Wojciech Sipak <[email protected]>
@wsipak wsipak marked this pull request as ready for review November 7, 2024 15:17
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github-actions bot commented Nov 7, 2024

Links to coverage and verification reports for this PR (#259) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

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github-actions bot commented Nov 7, 2024

Links to coverage and verification reports for this PR (#259) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

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Export DMI enable/active signals for core TAP accesses
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