Lint

bristol/test2.txt

@@ -0,0 +1,44 @@
+40 57
+3 1 8 8
+2 1 8
+
+2 1 0 8 17 AND
+2 1 0 8 18 XOR
+2 1 18 16 19 AND
+2 1 17 19 21 OR
+2 1 21 7 22 AND
+2 1 21 7 23 XOR
+2 1 23 15 24 AND
+2 1 22 24 26 OR
+2 1 26 6 27 AND
+2 1 26 6 28 XOR
+2 1 28 14 29 AND
+2 1 27 29 31 OR
+2 1 31 5 32 AND
+2 1 31 5 33 XOR
+2 1 33 13 34 AND
+2 1 32 34 36 OR
+2 1 36 4 37 AND
+2 1 36 4 38 XOR
+2 1 38 12 39 AND
+2 1 37 39 41 OR
+2 1 41 3 42 AND
+2 1 41 3 43 XOR
+2 1 43 11 44 AND
+2 1 42 44 46 OR
+2 1 46 2 47 AND
+2 1 46 2 20 XOR
+2 1 20 10 25 AND
+2 1 47 25 45 OR
+2 1 45 1 40 AND
+2 1 45 1 35 XOR
+2 1 35 9 30 AND
+2 1 40 30 48 OR
+2 1 35 9 49 XOR
+2 1 20 10 50 XOR
+2 1 43 11 51 XOR
+2 1 38 12 52 XOR
+2 1 33 13 53 XOR
+2 1 28 14 54 XOR
+2 1 23 15 55 XOR
+2 1 18 16 56 XOR

src/circuit.rs

@@ -1,13 +1,17 @@
 use std::collections::HashMap;
 
-use crate::{traits::{gate::GateTrait, circuit::CircuitTrait}, gates::{NotGate, AndGate, XorGate}, wire::Wire};
 use crate::utils::read_lines;
+use crate::{
+    gates::{AndGate, NotGate, XorGate},
+    traits::{circuit::CircuitTrait, gate::GateTrait},
+    wire::Wire,
+};
 
 pub struct Circuit {
     pub input_sizes: Vec<usize>,
     pub output_sizes: Vec<usize>,
     pub gates: Vec<Box<dyn GateTrait>>,
-    pub wires: Vec<Wire>
+    pub wires: Vec<Wire>,
 }
 
 impl Circuit {
@@ -17,14 +21,12 @@ impl Circuit {
             output_sizes: vec![32],
             gates: vec![Box::new(NotGate::new(vec![], vec![]))],
             wires: vec![],
-        }
+        };
     }
 }
 
 impl CircuitTrait for Circuit {
-    fn evaluate(&self) {
-
-    }
+    fn evaluate(&self) {}
 
     fn from_bristol(file: &str) -> Self {
         let mut nog: usize = 0; // number of gates
@@ -40,51 +42,59 @@ impl CircuitTrait for Circuit {
                     let mut words = line_str.split_whitespace();
                     nog = words.next().unwrap().parse().unwrap();
                     now = words.next().unwrap().parse().unwrap();
-                }
-                else if i == 1 {
+                } else if i == 1 {
                     let mut words = line_str.split_whitespace();
                     for _ in 0..words.next().unwrap().parse().unwrap() {
                         let x: usize = words.next().unwrap().parse().unwrap();
                         input_sizes.push(x);
                     }
-                }
-                else if i == 2 {
+                } else if i == 2 {
                     let mut words = line_str.split_whitespace();
                     for _ in 0..words.next().unwrap().parse().unwrap() {
                         let x: usize = words.next().unwrap().parse().unwrap();
                         output_sizes.push(x);
                     }
-                }
-                else if line_str != "" {
+                } else if line_str != "" {
                     let mut words = line_str.split_whitespace();
                     let noi = words.next().unwrap().parse().unwrap(); // number of inputs
                     let noo = words.next().unwrap().parse().unwrap(); // number of outputs
-                    let input_wires = (0..noi).map(|_| wire_indices.entry(words.next().unwrap().parse::<usize>().unwrap()).or_insert(Wire::new()).to_owned()).collect();
-                    let output_wires = (0..noo).map(|_| wire_indices.entry(words.next().unwrap().parse::<usize>().unwrap()).or_insert(Wire::new()).to_owned()).collect();
+                    let input_wires = (0..noi)
+                        .map(|_| {
+                            wire_indices
+                                .entry(words.next().unwrap().parse::<usize>().unwrap())
+                                .or_insert(Wire::new())
+                                .to_owned()
+                        })
+                        .collect();
+                    let output_wires = (0..noo)
+                        .map(|_| {
+                            wire_indices
+                                .entry(words.next().unwrap().parse::<usize>().unwrap())
+                                .or_insert(Wire::new())
+                                .to_owned()
+                        })
+                        .collect();
                     let gate_type = words.next().unwrap();
-                    
+
                     if gate_type.to_lowercase() == "not" {
                         let gate = NotGate {
                             input_wires,
                             output_wires,
                         };
                         gates.push(Box::new(gate));
-                    }
-                    else if gate_type.to_lowercase() == "and" {
+                    } else if gate_type.to_lowercase() == "and" {
                         let gate = AndGate {
                             input_wires,
                             output_wires,
                         };
                         gates.push(Box::new(gate));
-                    }
-                    else if gate_type.to_lowercase() == "xor" {
+                    } else if gate_type.to_lowercase() == "xor" {
                         let gate = XorGate {
                             input_wires,
                             output_wires,
                         };
                         gates.push(Box::new(gate));
-                    }
-                    else {
+                    } else {
                         panic!("unknown gate type");
                     }
                 }
@@ -100,12 +110,10 @@ impl CircuitTrait for Circuit {
             output_sizes,
             gates,
             wires: wire_indices.values().cloned().collect::<Vec<Wire>>(),
-        }
+        };
     }
 
-    fn generate_commitment_tree(&self) {
-
-    }
+    fn generate_commitment_tree(&self) {}
 }
 
 #[cfg(test)]
@@ -124,4 +132,3 @@ mod tests {
         assert!(circuit.output_sizes[0] == 64);
     }
 }
-

src/gates.rs

@@ -1,4 +1,4 @@
-use crate::{wire::Wire, traits::gate::GateTrait};
+use crate::{traits::gate::GateTrait, wire::Wire};
 
 // Every gate has a type parameter COM, which is a bit commitment scheme which can be hash based or schnorr based.
 // Every gate has an array of input wire pointers.
@@ -12,7 +12,7 @@ impl NotGate {
         return NotGate {
             input_wires,
             output_wires,
-        }
+        };
     }
 }
 
@@ -32,7 +32,7 @@ impl AndGate {
         return AndGate {
             input_wires,
             output_wires,
-        }
+        };
     }
 }
 
@@ -52,7 +52,7 @@ impl XorGate {
         return XorGate {
             input_wires,
             output_wires,
-        }
+        };
     }
 }
 

src/lib.rs

@@ -1,5 +1,5 @@
-pub mod traits;
-pub mod gates;
-pub mod wire;
 pub mod circuit;
+pub mod gates;
+pub mod traits;
 pub mod utils;
+pub mod wire;

src/main.rs

@@ -4,5 +4,4 @@ fn main() {
     println!("Hello, world!");
     let circuit = Circuit::from_bristol("bristol/add.txt");
     println!("{}", circuit.input_sizes[0]);
-
 }