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Releases: cepdnaclk/e20-co502-RV32IM_Pipelined_Processor_Group-03

V1.1

14 Dec 18:56
@Devin-Hasnaka Devin-Hasnaka
V1.1
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V1.1 Pre-release
Pre-release

Version 1 of initial stage includes basic functional modules such as ALU, register file, PC, mux. These modules are coded in Verilog and tested orcodingly.

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