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Merge pull request #23 from cepdnaclk/main
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30/12
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@samadhisakunika
samadhisakunika authored Dec 30, 2024
2 parents aa52c80 + 8c48a38 commit 3bae7bc
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Showing 13 changed files with 686 additions and 141 deletions.
6 changes: 4 additions & 2 deletions ALUunit/ALU.v
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
// ALU unit

module alu (data1,data2,opcode,Output);
module alu (data1,data2,ALU_OPCODE,Output);
input [31:0] data1,data2;
input [4:0] opcode;
input [4:0] ALU_OPCODE;

output reg [31:0] Output;

Expand All @@ -20,6 +20,7 @@ module alu (data1,data2,opcode,Output);


always @(*) begin

case (opcode)
5'b00000:#2 Output = data1+data2; //ADD instruction
5'b00001:#2 Output = data1-data2; //SUB instruction
Expand All @@ -40,6 +41,7 @@ module alu (data1,data2,opcode,Output);
5'b10000:#2 Output = (data1<data2)?32'b1:32'b0; //SLT instruction
5'b10001:#1 Output = data2; //Forwarding instruction
default:#1 Output = 32'b0;

endcase
end

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290 changes: 290 additions & 0 deletions ALUunit/ALUResult.vvp
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Original file line number Diff line number Diff line change
@@ -0,0 +1,290 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_0000013f212fb560 .scope module, "tb_ALU" "tb_ALU" 2 4;
.timescale -12 -12;
v0000013f212ec650_0 .var "ALU_OPCODE", 4 0;
v0000013f212ec6f0_0 .net "ALU_OUTPUT", 31 0, v0000013f212ec470_0; 1 drivers
v0000013f212ec790_0 .var "DATA1", 31 0;
v0000013f212eb930_0 .var "DATA2", 31 0;
v0000013f21351eb0_0 .var/i "i", 31 0;
S_0000013f212fb6f0 .scope module, "test_unit" "alu" 2 11, 3 3 0, S_0000013f212fb560;
.timescale 0 0;
.port_info 0 /INPUT 32 "data1";
.port_info 1 /INPUT 32 "data2";
.port_info 2 /INPUT 5 "ALU_OPCODE";
.port_info 3 /OUTPUT 32 "Output";
v0000013f212ebb10_0 .net "ALU_OPCODE", 4 0, v0000013f212ec650_0; 1 drivers
v0000013f212ec330_0 .net "MULHSU_result", 31 0, L_0000013f21352950; 1 drivers
v0000013f212ec830_0 .net "MULHU_result", 31 0, L_0000013f21352c70; 1 drivers
v0000013f212ebbb0_0 .net "MULH_result", 31 0, L_0000013f21351d70; 1 drivers
v0000013f212ec470_0 .var "Output", 31 0;
v0000013f212ebe30_0 .net/s *"_ivl_0", 63 0, L_0000013f21352310; 1 drivers
L_0000013f21353018 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000013f212ec290_0 .net *"_ivl_11", 31 0, L_0000013f21353018; 1 drivers
v0000013f212ec150_0 .net *"_ivl_12", 63 0, L_0000013f21351410; 1 drivers
L_0000013f21353060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000013f212ec010_0 .net *"_ivl_15", 31 0, L_0000013f21353060; 1 drivers
v0000013f212ebd90_0 .net/s *"_ivl_2", 63 0, L_0000013f21351f50; 1 drivers
v0000013f212ec510_0 .net *"_ivl_20", 63 0, L_0000013f21351a50; 1 drivers
L_0000013f213530a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000013f212eb9d0_0 .net *"_ivl_23", 31 0, L_0000013f213530a8; 1 drivers
v0000013f212ec5b0_0 .net *"_ivl_24", 63 0, L_0000013f21351910; 1 drivers
L_0000013f213530f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000013f212eba70_0 .net *"_ivl_27", 31 0, L_0000013f213530f0; 1 drivers
v0000013f212ebc50_0 .net *"_ivl_8", 63 0, L_0000013f213523b0; 1 drivers
v0000013f212ec3d0_0 .net "data1", 31 0, v0000013f212ec790_0; 1 drivers
v0000013f212ebed0_0 .net "data2", 31 0, v0000013f212eb930_0; 1 drivers
v0000013f212ec1f0_0 .net "mulh_result", 63 0, L_0000013f213524f0; 1 drivers
v0000013f212ebf70_0 .net "mulhsu_result", 63 0, L_0000013f21351050; 1 drivers
v0000013f212ec0b0_0 .net "mulhu_result", 63 0, L_0000013f21351c30; 1 drivers
E_0000013f212ee640/0 .event anyedge, v0000013f212ebb10_0, v0000013f212ec3d0_0, v0000013f212ebed0_0, v0000013f212ebbb0_0;
E_0000013f212ee640/1 .event anyedge, v0000013f212ec830_0, v0000013f212ec330_0;
E_0000013f212ee640 .event/or E_0000013f212ee640/0, E_0000013f212ee640/1;
L_0000013f21352310 .extend/s 64, v0000013f212ec790_0;
L_0000013f21351f50 .extend/s 64, v0000013f212eb930_0;
L_0000013f213524f0 .arith/mult 64, L_0000013f21352310, L_0000013f21351f50;
L_0000013f21351d70 .part L_0000013f213524f0, 32, 32;
L_0000013f213523b0 .concat [ 32 32 0 0], v0000013f212ec790_0, L_0000013f21353018;
L_0000013f21351410 .concat [ 32 32 0 0], v0000013f212eb930_0, L_0000013f21353060;
L_0000013f21351c30 .arith/mult 64, L_0000013f213523b0, L_0000013f21351410;
L_0000013f21352c70 .part L_0000013f21351c30, 32, 32;
L_0000013f21351a50 .concat [ 32 32 0 0], v0000013f212ec790_0, L_0000013f213530a8;
L_0000013f21351910 .concat [ 32 32 0 0], v0000013f212eb930_0, L_0000013f213530f0;
L_0000013f21351050 .arith/mult 64, L_0000013f21351a50, L_0000013f21351910;
L_0000013f21352950 .part L_0000013f21351050, 32, 32;
.scope S_0000013f212fb6f0;
T_0 ;
%wait E_0000013f212ee640;
%load/vec4 v0000013f212ebb10_0;
%dup/vec4;
%pushi/vec4 0, 0, 5;
%cmp/u;
%jmp/1 T_0.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 5;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 5;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 5;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 5;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 5, 0, 5;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 6, 0, 5;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 7, 0, 5;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 8, 0, 5;
%cmp/u;
%jmp/1 T_0.8, 6;
%dup/vec4;
%pushi/vec4 9, 0, 5;
%cmp/u;
%jmp/1 T_0.9, 6;
%dup/vec4;
%pushi/vec4 10, 0, 5;
%cmp/u;
%jmp/1 T_0.10, 6;
%dup/vec4;
%pushi/vec4 11, 0, 5;
%cmp/u;
%jmp/1 T_0.11, 6;
%dup/vec4;
%pushi/vec4 12, 0, 5;
%cmp/u;
%jmp/1 T_0.12, 6;
%dup/vec4;
%pushi/vec4 13, 0, 5;
%cmp/u;
%jmp/1 T_0.13, 6;
%dup/vec4;
%pushi/vec4 14, 0, 5;
%cmp/u;
%jmp/1 T_0.14, 6;
%dup/vec4;
%pushi/vec4 15, 0, 5;
%cmp/u;
%jmp/1 T_0.15, 6;
%dup/vec4;
%pushi/vec4 16, 0, 5;
%cmp/u;
%jmp/1 T_0.16, 6;
%dup/vec4;
%pushi/vec4 17, 0, 5;
%cmp/u;
%jmp/1 T_0.17, 6;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.0 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%add;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.1 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%sub;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.2 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%or;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.3 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%xor;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.4 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%and;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.5 ;
%load/vec4 v0000013f212ec3d0_0;
%ix/getv 4, v0000013f212ebed0_0;
%shiftr 4;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.6 ;
%load/vec4 v0000013f212ec3d0_0;
%ix/getv 4, v0000013f212ebed0_0;
%shiftl 4;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.7 ;
%load/vec4 v0000013f212ec3d0_0;
%ix/getv 4, v0000013f212ebed0_0;
%shiftr 4;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.8 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%mul;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.9 ;
%load/vec4 v0000013f212ebbb0_0;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.10 ;
%load/vec4 v0000013f212ec830_0;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.11 ;
%load/vec4 v0000013f212ec330_0;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.12 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%div/s;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.13 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%div;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.14 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%mod/s;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.15 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%mod;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.16 ;
%load/vec4 v0000013f212ec3d0_0;
%load/vec4 v0000013f212ebed0_0;
%cmp/u;
%flag_mov 8, 5;
%jmp/0 T_0.20, 8;
%pushi/vec4 1, 0, 32;
%jmp/1 T_0.21, 8;
T_0.20 ; End of true expr.
%pushi/vec4 0, 0, 32;
%jmp/0 T_0.21, 8;
; End of false expr.
%blend;
T_0.21;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.17 ;
%load/vec4 v0000013f212ebed0_0;
%store/vec4 v0000013f212ec470_0, 0, 32;
%jmp T_0.19;
T_0.19 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
.scope S_0000013f212fb560;
T_1 ;
%vpi_call 2 13 "$monitor", "Time=%0t, Data1=%d, Data2=%d, Output=%d", $time, v0000013f212ec790_0, v0000013f212eb930_0, v0000013f212ec6f0_0 {0 0 0};
%pushi/vec4 6, 0, 32;
%store/vec4 v0000013f212ec790_0, 0, 32;
%pushi/vec4 3, 0, 32;
%store/vec4 v0000013f212eb930_0, 0, 32;
%pushi/vec4 0, 0, 5;
%store/vec4 v0000013f212ec650_0, 0, 5;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000013f21351eb0_0, 0, 32;
T_1.0 ;
%load/vec4 v0000013f21351eb0_0;
%cmpi/s 17, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_1.1, 5;
%load/vec4 v0000013f21351eb0_0;
%pad/s 5;
%store/vec4 v0000013f212ec650_0, 0, 5;
%delay 5, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0000013f21351eb0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0000013f21351eb0_0, 0, 32;
%jmp T_1.0;
T_1.1 ;
%vpi_call 2 26 "$finish" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"ALUtestbench.v";
"ALU.v";
8 changes: 4 additions & 4 deletions ALUunit/ALUtestbench.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3,24 +3,24 @@

module tb_ALU ;
reg[31:0]DATA1,DATA2;
reg[4:0]OPCODE;
reg[4:0]ALU_OPCODE;
wire[31:0]ALU_OUTPUT;

integer i;

alu test_unit(DATA1,DATA2,OPCODE,ALU_OUTPUT); // initiating the alu module
alu test_unit(DATA1,DATA2,ALU_OPCODE,ALU_OUTPUT); // initiating the alu module
initial begin
$monitor("Time=%0t, Data1=%d, Data2=%d, Output=%d", $time, DATA1, DATA2,ALU_OUTPUT);


DATA1 = 32'd6;
DATA2 = 32'd3;
OPCODE = 5'd0;
ALU_OPCODE = 5'd0;


for (i=0;i<=17;i++)
begin
OPCODE =i;
ALU_OPCODE =i;
#5;
end
$finish;
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