Merge pull request #14 from cepdnaclk/Samadhi

Samadhi
cepdnaclk · Dec 13, 2024 · 3b7a00b · 3b7a00b
2 parents 2659b93 + 8209e65
commit 3b7a00b
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Showing 2 changed files with 27 additions and 26 deletions.
diff --git a/ALUunit/ALU.v b/ALUunit/ALU.v
@@ -21,25 +21,25 @@ module alu (data1,data2,opcode,Output);
 
     always @(*) begin
         case (opcode)
-            5'b00000:Output = data1+data2;                          //ADD instruction
-            5'b00001:Output = data1-data2;                          //SUB instruction
-            5'b00010:Output = data1|data2;                          //OR instruction
-            5'b00011:Output = data1^data2;                          //XOR instruction
-            5'b00100:Output = data1&data2;                          //AND instruction
-            5'b00101:Output = data1>>data2;                         //SLR instruction
-            5'b00110:Output = data1<<data2;                         //SLL instruction
-            5'b00111:Output = data1>>>data2;                        //SRA instruction
-            5'b01000:Output = data1*data2;                          //MUL instruction
-            5'b01001:Output = MULH_result;                          //MULH instruction
-            5'b01010:Output = MULHU_result;                         //MULHU instruction
-            5'b01011:Output = MULHSU_result;                        //MULHSU instruction
-            5'b01100:Output = $signed(data1)/$signed(data2);        //DIV instruction
-            5'b01101:Output = $unsigned(data1)/$unsigned(data2);    //DIVH instruction
-            5'b01110:Output = $signed(data1)% $signed(data2);       //REM instuction
-            5'b01111:Output = $unsigned(data1)% $unsigned(data2);   //REMU instruction
-            5'b10000:Output = (data1<data2)?32'b1:32'b0;            //SLT instruction
-            5'b10001:Output = data2;                                //Forwarding instruction
-            default:Output = 32'b0;
+            5'b00000:#2 Output = data1+data2;                          //ADD instruction
+            5'b00001:#2 Output = data1-data2;                          //SUB instruction
+            5'b00010:#1 Output = data1|data2;                          //OR instruction
+            5'b00011:#1 Output = data1^data2;                          //XOR instruction
+            5'b00100:#1 Output = data1&data2;                          //AND instruction
+            5'b00101:#2 Output = data1>>data2;                         //SLR instruction
+            5'b00110:#2 Output = data1<<data2;                         //SLL instruction
+            5'b00111:#2 Output = data1>>>data2;                        //SRA instruction
+            5'b01000:#3 Output = data1*data2;                          //MUL instruction
+            5'b01001:#3 Output = MULH_result;                          //MULH instruction
+            5'b01010:#3 Output = MULHU_result;                         //MULHU instruction
+            5'b01011:#3 Output = MULHSU_result;                        //MULHSU instruction
+            5'b01100:#3 Output = $signed(data1)/$signed(data2);        //DIV instruction
+            5'b01101:#3 Output = $unsigned(data1)/$unsigned(data2);    //DIVH instruction
+            5'b01110:#4 Output = $signed(data1)% $signed(data2);       //REM instuction
+            5'b01111:#4 Output = $unsigned(data1)% $unsigned(data2);   //REMU instruction
+            5'b10000:#2 Output = (data1<data2)?32'b1:32'b0;            //SLT instruction
+            5'b10001:#1 Output = data2;                                //Forwarding instruction
+            default:#1 Output = 32'b0;
         endcase
     end
 

diff --git a/BranchController/BranchController.v b/BranchController/BranchController.v
@@ -11,16 +11,17 @@ module BranchController (data1,data2,func3,ALUresult,Branch,Jump,TargetedAddress
         if (Branch==1'b1) begin 
             TargetedAddress = ALUresult;
             case (func3)
-                3'b000:PCAddressController=(data1==data2)?1'b1:1'b0;                            //BEQ instruction
-                3'b001:PCAddressController=(data1!=data2)?1'b1:1'b0;                            //BNE instruction
-                3'b100:PCAddressController=($signed(data1)<$signed(data2))?1'b1:1'b0;           //BLT instruction
-                3'b101:PCAddressController=($signed(data1)>=$signed(data2))?1'b1:1'b0;          //BGE instruction
-                3'b110:PCAddressController=($unsigned(data1)<$unsigned(data2))?1'b1:1'b0;       //BLTU instruction
-                3'b111:PCAddressController=($unsigned(data1)>=$unsigned(data2))?1'b1:1'b0;      //BGEU instruction
-                default: PCAddressController=1'b0;
+                3'b000:#1 PCAddressController=(data1==data2)?1'b1:1'b0;                            //BEQ instruction
+                3'b001:#1 PCAddressController=(data1!=data2)?1'b1:1'b0;                            //BNE instruction
+                3'b100:#1 PCAddressController=($signed(data1)<$signed(data2))?1'b1:1'b0;           //BLT instruction
+                3'b101:#1 PCAddressController=($signed(data1)>=$signed(data2))?1'b1:1'b0;          //BGE instruction
+                3'b110:#1 PCAddressController=($unsigned(data1)<$unsigned(data2))?1'b1:1'b0;       //BLTU instruction
+                3'b111:#1 PCAddressController=($unsigned(data1)>=$unsigned(data2))?1'b1:1'b0;      //BGEU instruction
+                default: #1 PCAddressController=1'b0;
             endcase    
         end
         if (Jump==1'b1) begin
+            #1;
             TargetedAddress =ALUresult;
             PCAddressController =1'b1;                                                          //Jump Insruction
         end