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| Original file line number | Diff line number | Diff line change |
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@@ -28581,18 +28654,18 @@ | |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| { | ||
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8 changes: 4 additions & 4 deletions
8
...pipeline-implementation-group2/index.json → ...ipeline-implementation-group-2/index.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,14 +1,14 @@ | ||
| { | ||
| "title": "RV32IM pipeline implementation group2", | ||
| "title": "RV32IM pipeline implementation group 2", | ||
| "description": "This Git repository contains the implementation of a RISC32IM processor pipeline using Verilog. The pipeline includes stages for instruction fetch, decode, execute, memory access, and write-back. The implementation includes a testbench for verification.", | ||
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| }, | ||
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