Merge pull request intel#191 from edwarddavidbaker/sync-platforms

ADL: Release event updates
captain5050 · May 29, 2024 · 6891f3b · 6891f3b
2 parents f74babd + ea4f309
commit 6891f3b
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diff --git a/ADL/events/alderlake_goldencove_core.json b/ADL/events/alderlake_goldencove_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.26",
-    "DatePublished": "04/03/2024",
-    "Version": "1.26",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.27",
+    "DatePublished": "05/22/2024",
+    "Version": "1.27",
     "Legend": ""
   },
   "Events": [
@@ -787,6 +787,58 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x02",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
+      "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
+      "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x02",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+      "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
+      "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x20",
       "UMask": "0x04",
@@ -943,6 +995,58 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x21",
+      "UMask": "0x02",
+      "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
+      "BriefDescription": "Cacheable and noncacheable code read requests",
+      "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x21",
+      "UMask": "0x04",
+      "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
+      "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
+      "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x21",
       "UMask": "0x08",
@@ -1021,6 +1125,32 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x23",
+      "UMask": "0x40",
+      "EventName": "L2_TRANS.L2_WB",
+      "BriefDescription": "L2 writebacks that access L2 cache",
+      "PublicDescription": "Counts L2 writebacks that access L2 cache.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x24",
       "UMask": "0x21",
@@ -2945,6 +3075,32 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x80",
+      "UMask": "0x04",
+      "EventName": "ICACHE_DATA.STALL_PERIODS",
+      "BriefDescription": "ICACHE_DATA.STALL_PERIODS",
+      "PublicDescription": "ICACHE_DATA.STALL_PERIODS",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "500009",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "1",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x83",
       "UMask": "0x04",
@@ -4115,6 +4271,32 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xae",
+      "UMask": "0x01",
+      "EventName": "UOPS_ISSUED.CYCLES",
+      "BriefDescription": "UOPS_ISSUED.CYCLES",
+      "PublicDescription": "UOPS_ISSUED.CYCLES",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xb0",
       "UMask": "0x01",
@@ -6793,6 +6975,32 @@
       "PDISTCounter": "NA",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xcd",
+      "UMask": "0x01",
+      "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
+      "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
+      "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency.",
+      "Counter": "1,2,3,4,5,6,7",
+      "PEBScounters": "1,2,3,4,5,6,7",
+      "SampleAfterValue": "53",
+      "MSRIndex": "0x3F6",
+      "MSRValue": "0x400",
+      "Precise": "1",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "2",
+      "Data_LA": "1",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xcd",
       "UMask": "0x02",

diff --git a/ADL/events/alderlake_gracemont_core.json b/ADL/events/alderlake_gracemont_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.26",
-    "DatePublished": "04/03/2024",
-    "Version": "1.26",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.27",
+    "DatePublished": "05/22/2024",
+    "Version": "1.27",
     "Legend": ""
   },
   "Events": [
@@ -501,12 +501,38 @@
       "PDISTCounter": "NA",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x0e",
+      "UMask": "0x00",
+      "EventName": "UOPS_ISSUED.ANY",
+      "BriefDescription": "Counts the number of uops issued by the front end every cycle.",
+      "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued.",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x2e",
       "UMask": "0x41",
       "EventName": "LONGEST_LAT_CACHE.MISS",
       "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
-      "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+      "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
       "Counter": "0,1,2,3,4,5",
       "PEBScounters": "0,1,2,3,4,5",
       "SampleAfterValue": "200003",
@@ -532,7 +558,7 @@
       "UMask": "0x4f",
       "EventName": "LONGEST_LAT_CACHE.REFERENCE",
       "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
-      "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+      "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
       "Counter": "0,1,2,3,4,5",
       "PEBScounters": "0,1,2,3,4,5",
       "SampleAfterValue": "200003",
@@ -1489,6 +1515,32 @@
       "PDISTCounter": "NA",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x75",
+      "UMask": "0x04",
+      "EventName": "SERIALIZATION.C01_MS_SCB",
+      "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
+      "PublicDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "NA",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x80",
       "UMask": "0x02",
@@ -3283,6 +3335,32 @@
       "PDISTCounter": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xd0",
+      "UMask": "0x21",
+      "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
+      "BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
+      "PublicDescription": "Counts the number of load uops retired that performed one or more locks.",
+      "Counter": "0,1,2,3,4,5",
+      "PEBScounters": "0,1,2,3,4,5",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "1",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "1",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xd0",
       "UMask": "0x41",