feat:add port for cygnet (STM32L433)

ports/stm/boards/STM32L433_boot.ld

@@ -0,0 +1,38 @@
+/*
+    GNU linker script for STM32L433 with bootloader
+*/
+
+/* Specify the memory areas */
+/*
+MEMORY
+{
+    FLASH (rx)          : ORIGIN = 0x08000000, LENGTH = 256k
+    FLASH_ISR (rx)      : ORIGIN = 0x08010000, LENGTH = 4K
+    FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 156K-64K-4K
+    FLASH_FS (rw)       : ORIGIN = 0x08027000, LENGTH = 88K
+    RAM (xrw)           : ORIGIN = 0x20000000, LENGTH = 64K
+}
+*/
+
+MEMORY
+{
+    FLASH (rx)          : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
+    FLASH_ISR (rx)      : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
+    FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 1024K-128K-64K-4K  /* For now, limit to 1MB so that bank switching is still possible. */
+    FLASH_FS (rw)       : ORIGIN = 0x08100000, LENGTH = 1024K
+    RAM (xrw)           : ORIGIN = 0x20000000, LENGTH = 640K
+}
+
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 24K;
+_minimum_heap_size = 16K;
+
+/* Define the top end of the stack.  The stack is full descending so begins just
+   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+   aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);

ports/stm/boards/STM32L433_default.ld

@@ -0,0 +1,33 @@
+/*
+    GNU linker script for STM32L433 with filesystem
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)          : ORIGIN = 0x08000000, LENGTH = 256K /* entire flash */
+    FLASH_ISR (rx)      : ORIGIN = 0x08000000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
+    /*
+    FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 60K
+    FLASH_FS (rw)       : ORIGIN = 0x08010000, LENGTH = 60K
+    */
+    FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 4K
+    FLASH_FS (rw)       : ORIGIN = 0x08004000, LENGTH = 60K
+    RAM (xrw)           : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 24K;
+_minimum_heap_size = 16K;
+
+/* Define the top end of the stack.  The stack is full descending so begins just
+   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+   aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+
+/* ensure the firmware is within bounds */
+ASSERT ( (ORIGIN(FLASH_FIRMWARE) + LENGTH(FLASH_FIRMWARE)) <= (ORIGIN(FLASH)+LENGTH(FLASH)), "FLASH_FIRMWARE out of bounds" );

ports/stm/boards/STM32L4R5_default.ld

@@ -16,7 +16,7 @@ MEMORY
 _minimum_stack_size = 24K;
 _minimum_heap_size = 16K;
 
-/* Define tho top end of the stack.  The stack is full descending so begins just
+/* Define the top end of the stack.  The stack is full descending so begins just
    above last byte of RAM.  Note that EABI requires the stack to be 8-byte
    aligned for a call. */
 _estack = ORIGIN(RAM) + LENGTH(RAM);

ports/stm/boards/cygnet/board.c

@@ -0,0 +1,75 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#include "supervisor/board.h"
+#include "mpconfigboard.h"
+
+#include "stm32l4xx.h"
+#include "stm32l433xx.h"
+
+#include "shared-bindings/microcontroller/Pin.h"
+#include "shared-bindings/digitalio/DigitalInOut.h"
+#include "shared-bindings/digitalio/Direction.h"
+#include "shared-bindings/digitalio/DriveMode.h"
+#include "board.h"
+
+digitalio_digitalinout_obj_t power_pin = { .base.type = &digitalio_digitalinout_type };
+digitalio_digitalinout_obj_t discharge_pin = { .base.type = &digitalio_digitalinout_type };
+
+void initialize_discharge_pin(void) {
+
+    /* Initialize the 3V3 discharge to be OFF and the output power to be ON */
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+
+
+    common_hal_digitalio_digitalinout_construct(&power_pin, &pin_PE04);
+    common_hal_digitalio_digitalinout_construct(&discharge_pin, &pin_PE06);
+    common_hal_digitalio_digitalinout_never_reset(&power_pin);
+    common_hal_digitalio_digitalinout_never_reset(&discharge_pin);
+
+    GPIO_InitTypeDef GPIO_InitStruct;
+    /* Set the DISCHARGE pin and the USB_DETECT pin to FLOAT */
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); /* PE6 DISCHRG */
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* PC6 is USB_DETECT */
+
+    /* Turn on the 3V3 regulator */
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_SET);
+
+}
+
+void board_init(void) {
+    // enable the debugger while sleeping. Todo move somewhere more central (kind of generally useful in a debug build)
+    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+
+    //  Set tick interrupt priority, default HAL value is intentionally invalid
+    //  Without this, USB does not function.
+    HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
+
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_SET);
+    HAL_Delay(50);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_RESET);
+}
+
+void reset_board(void) {
+    initialize_discharge_pin();
+}
+
+// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.

ports/stm/boards/cygnet/board.h

@@ -0,0 +1,12 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+#include "common-hal/digitalio/DigitalInOut.h"
+
+extern digitalio_digitalinout_obj_t power_pin;
+extern digitalio_digitalinout_obj_t discharge_pin;

ports/stm/boards/cygnet/mpconfigboard.h

@@ -0,0 +1,47 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2024 Blues Wireless Contributors.
+//
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+// Micropython setup
+
+#define MICROPY_HW_BOARD_NAME       "Cygnet"
+#define MICROPY_HW_MCU_NAME         "STM32L433CCT6"
+
+#define MICROPY_PY_SYS_PLATFORM     MICROPY_HW_BOARD_NAME
+
+#define STM32L433XX
+#define BOARD_CYGNET
+
+#define LSE_VALUE ((uint32_t)32768)
+#define BOARD_HAS_LOW_SPEED_CRYSTAL (1)
+#define BOARD_HAS_HIGH_SPEED_CRYSTAL (0)
+
+// Increase drive strength of 32kHz external crystal, in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58. LSE oscillator characteristics.
+// The drive strength RCC_LSEDRIVE_LOW is marginal for the 32kHz crystal oscillator stability, and RCC_LSEDRIVE_MEDIUMLOW meets the calculated drive strength with a small margin for parasitic capacitance.
+#define BOARD_LSE_DRIVE_LEVEL RCC_LSEDRIVE_MEDIUMLOW
+
+// Bootloader only
+#ifdef UF2_BOOTLOADER_ENABLED
+    #define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader
+#endif
+
+#define BOARD_NO_VBUS_SENSE (1)
+#define BOARD_NO_USB_OTG_ID_SENSE (1)
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PB06)
+#define DEFAULT_I2C_BUS_SDA (&pin_PB07)
+
+#define DEFAULT_SPI_BUS_SS (&pin_PB08)
+#define DEFAULT_SPI_BUS_SCK (&pin_PA05)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PB05)
+#define DEFAULT_SPI_BUS_MISO (&pin_PB06)
+
+#define DEFAULT_UART_BUS_RX (&pin_PA10)
+#define DEFAULT_UART_BUS_TX (&pin_PA09)
+
+#define CYGNET_DISCHARGE_3V3 (&pin_PH01)
+#define CYGNET_ENABLE_3V3 (&pin_PH00)

ports/stm/boards/cygnet/mpconfigboard.mk

@@ -0,0 +1,58 @@
+USB_VID = 0x30A4
+USB_PID = 0x03
+USB_PRODUCT = "Cygnet"
+USB_MANUFACTURER = "Blues Inc."
+
+MCU_SERIES = L4
+MCU_VARIANT = STM32L433xx
+MCU_PACKAGE = LQFP48
+
+LD_COMMON = boards/common_default.ld
+LD_DEFAULT = boards/STM32L433_default.ld
+# UF2 boot option
+LD_BOOT = boards/STM32L433_boot.ld
+UF2_OFFSET = 0x8010000
+UF2_BOOTLOADER ?= 1
+CIRCUITPY_BUILD_EXTENSIONS = bin,uf2
+
+INTERNAL_FLASH_FILESYSTEM = 1
+LONGINT_IMPL = NONE
+CIRCUITPY_FULL_BUILD = 0
+
+CIRCUITPY_ALARM = 0
+CIRCUITPY_ANALOGIO = 1
+CIRCUITPY_AUDIOBUSIO = 0
+CIRCUITPY_AUDIOBUSIO_I2SOUT = 0
+CIRCUITPY_AUDIOBUSIO_PDMIN = 0
+CIRCUITPY_AUDIOPWMIO = 0
+CIRCUITPY_BITBANGIO = 1
+CIRCUITPY_BLEIO = 0
+CIRCUITPY_BLEIO_HCI = 0
+CIRCUITPY_BUSDEVICE = 0
+CIRCUITPY_BUSIO = 1
+CIRCUITPY_CANIO = 0
+CIRCUITPY_DIGITALIO = 1
+CIRCUITPY_DISPLAYIO = 0
+CIRCUITPY_ENABLE_MPY_NATIVE = 1
+CIRCUITPY_I2CTARGET = 0
+CIRCUITPY_KEYPAD = 0
+CIRCUITPY_MICROCONTROLLER = 1
+CIRCUITPY_NEOPIXEL_WRITE = 0
+CIRCUITPY_NVM = 0
+CIRCUITPY_OS = 1
+CIRCUITPY_PIXELBUF = 0
+CIRCUITPY_PULSEIO = 1
+CIRCUITPY_PWMIO = 1
+CIRCUITPY_RANDOM = 1
+CIRCUITPY_REQUIRE_I2C_PULLUPS = 0
+CIRCUITPY_RGBMATRIX = 0
+CIRCUITPY_RTC = 1
+CIRCUITPY_SDCARDIO = 0
+CIRCUITPY_STORAGE = 1
+CIRCUITPY_TOUCHIO = 0
+CIRCUITPY_UDB_CDC = 1
+CIRCUITPY_ULAB = 1
+CIRCUITPY_USB_HID = 0
+CIRCUITPY_USB_MIDI = 0
+CIRCUITPY_USB_MSC = 1
+CIRCUITPY_USB_VENDOR = 1

ports/stm/boards/cygnet/pins.c

@@ -0,0 +1,108 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#include "py/objtuple.h"
+#include "shared-bindings/board/__init__.h"
+#include "board.h"
+
+// extended pins
+static const mp_rom_map_elem_t board_module_carrier_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PE01) },
+
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA04) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_CS), MP_ROM_PTR(&pin_PB08) },
+
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },
+
+    { MP_ROM_QSTR(MP_QSTR_EN), MP_ROM_PTR(&pin_PH00) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB14) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },
+};
+
+MP_DEFINE_CONST_DICT(board_module_carrier, board_module_carrier_table);
+
+MP_DEFINE_CONST_OBJ_TYPE(
+    carrier_type,
+    MP_QSTR_Ext,
+    MP_TYPE_FLAG_NONE,
+    locals_dict, &board_module_carrier
+    );
+
+
+// Core Feather Pins
+static const mp_rom_map_elem_t board_module_globals_table[] = {
+    CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
+
+    { MP_ROM_QSTR(MP_QSTR_ext), MP_ROM_PTR(&carrier_type) },
+
+    { MP_ROM_QSTR(MP_QSTR_ENABLE_3V3), &power_pin },
+    { MP_ROM_QSTR(MP_QSTR_DISCHARGE_3V3), &discharge_pin },
+
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA04) },
+
+    { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_SWITCH), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB02) },
+
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PE01) },
+
+    { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PB04) },   // ADC, PWM, DAC2 output also
+
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },    // PWM
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },    // PWM
+
+    { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) },   // D10
+    { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) },   // D13
+
+    { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA05) },
+
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },     // ADC, PWM
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },     // PWM
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);