riscv: make the debugger stop on ebreak

blackmagic-debug · Feb 2, 2024 · 06e07f2 · 06e07f2
1 parent 016b67d
commit 06e07f2
Showing 1 changed file with 7 additions and 4 deletions.
diff --git a/src/target/riscv_debug.c b/src/target/riscv_debug.c
@@ -107,9 +107,10 @@
 #define RV_VENDOR_JEP106_CONT_MASK 0x7fffff80U
 #define RV_VENDOR_JEP106_CODE_MASK 0x7fU
 
-#define RV_DCSR_STEP 0x00000004U
-#define RV_DCSR_CAUSE_MASK 0x000001c0U
-#define RV_DCSR_STEPIE 0x00000800U
+#define RV_DCSR_STEP 0x00000004U
+#define RV_DCSR_CAUSE_MASK 0x000001c0U
+#define RV_DCSR_STEPIE 0x00000800U
+#define RV_DCSR_EBREAK_MACHINE 0x00008000U
 
 #define RV_GPRS_COUNT 32U
 
@@ -832,8 +833,10 @@ static void riscv_halt_resume(target_s *target, const bool step)
  return;
  if (step)
  stepping_config |= RV_DCSR_STEP | RV_DCSR_STEPIE;
- else
+ else {
  stepping_config &= ~(RV_DCSR_STEP | RV_DCSR_STEPIE);
+ stepping_config |= RV_DCSR_EBREAK_MACHINE;
+ }
  if (!riscv_csr_write(hart, RV_DCSR | RV_CSR_FORCE_32_BIT, &stepping_config))
  return;
  /* Request the hart to resume */