Skip to content

baldandbrave/MIPSCOEN6741

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

108 Commits
.gitignore
.gitignore
 
 
ALU.vhd
ALU.vhd
 
 
ALUControl.vhd
ALUControl.vhd
 
 
Adder.vhd
Adder.vhd
 
 
ControlHazardUnit.vhd
ControlHazardUnit.vhd
 
 
Controller.vhd
Controller.vhd
 
 
DataHazardUnit.vhd
DataHazardUnit.vhd
 
 
DataMemory.vhd
DataMemory.vhd
 
 
EX_MEM.vhd
EX_MEM.vhd
 
 
ID_EX.vhd
ID_EX.vhd
 
 
IF_ID.vhd
IF_ID.vhd
 
 
InstructionMemory.vhd
InstructionMemory.vhd
 
 
InstructionMemory_Simulation_ModelSim.PNG
InstructionMemory_Simulation_ModelSim.PNG
 
 
LICENSE
LICENSE
 
 
MEM_WB.vhd
MEM_WB.vhd
 
 
MIPS.cr.mti
MIPS.cr.mti
 
 
MIPS.do
MIPS.do
 
 
MIPS.mpf
MIPS.mpf
 
 
MIPS.vhd
MIPS.vhd
 
 
Mux32.vhd
Mux32.vhd
 
 
MuxNBit.vhd
MuxNBit.vhd
 
 
Mux_Tb.png
Mux_Tb.png
 
 
Mux_Tb_5bit.png
Mux_Tb_5bit.png
 
 
PC.vhd
PC.vhd
 
 
README.md
README.md
 
 
Registers.vhd
Registers.vhd
 
 
ShiftLeft.vhd
ShiftLeft.vhd
 
 
SignExtend.vhd
SignExtend.vhd
 
 
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.Apr.2006_Part1.pdf
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.Apr.2006_Part1.pdf
 
 
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.Apr.2006_Part2.pdf
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.Apr.2006_Part2.pdf
 
 
tb_ALU.png
tb_ALU.png
 
 
tb_ALU.vhd
tb_ALU.vhd
 
 
tb_ALUControl.png
tb_ALUControl.png
 
 
tb_ALUControl.vhd
tb_ALUControl.vhd
 
 
tb_ControlHazardUnit.png
tb_ControlHazardUnit.png
 
 
tb_ControlHazardUnit.vhd
tb_ControlHazardUnit.vhd
 
 
tb_DataHazardUnit.png
tb_DataHazardUnit.png
 
 
tb_DataHazardUnit.vhd
tb_DataHazardUnit.vhd
 
 
tb_DataMemory.png
tb_DataMemory.png
 
 
tb_DataMemory.vhd
tb_DataMemory.vhd
 
 
tb_IF_ID.png
tb_IF_ID.png
 
 
tb_IF_ID.vhd
tb_IF_ID.vhd
 
 
tb_InstructionMemory.vhd
tb_InstructionMemory.vhd
 
 
tb_Mux32.vhd
tb_Mux32.vhd
 
 
tb_PC.png
tb_PC.png
 
 
tb_PC.vhd
tb_PC.vhd
 
 
wave_ALU.do
wave_ALU.do
 
 
wave_ControlHazardUnit.do
wave_ControlHazardUnit.do
 
 
wave_DataHazardUnit.do
wave_DataHazardUnit.do
 
 
wave_IF_ID.do
wave_IF_ID.do
 
 
wave_PC.do
wave_PC.do
 
 
wlftnhn1v1
wlftnhn1v1
 
 
wlftw1eqbw
wlftw1eqbw
 
 

Repository files navigation

MIPS

MIPS Processor Design for COEN6741

Do Not copy the code, drop this class ASAP.

Project Requirements

  • 32 bit pipelined MIPS
  • Implement 10 instructions: and sub xor andi subi add beq lw sw jr
  • Structural harzards free, data harzard and control harzard handled by stalling

Special thanks! Most of components originated from here

https://github.com/dugagjin/MIPS

Useful Repositories

https://github.com/PiJoules/MIPS-processor

https://github.com/cm4233/MIPS-Processor-VHDL/tree/master/VHDL%20Codes

https://github.com/BYVoid/MIPS32

Opcode References

https://opencores.org/projects/plasma/opcodes

Reference for ALUOp

http://fourier.eng.hmc.edu/e85_old/lectures/processor/node5.html

MIPS Conventional Registers Structure

http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s03.html

Convert Instructions to Hex format

http://www.kurtm.net/mipsasm/index.cgi

About

MIPS Processor Design for COEN6741

Resources

Readme

License

GPL-3.0 license
Activity

Stars

0 stars

Watchers

1 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Contributors 4

  •  
  •  
  •  
  •  

Languages